From 00a220877c8fc27f161017e68b67fce23117c0ad Mon Sep 17 00:00:00 2001
From: Marshall Dawson <marshalldawson3rd@gmail.com>
Date: Mon, 20 Jan 2020 23:05:31 -0700
Subject: soc/amd/picasso: Add FSP support for including AGESA

AMD has rewritten AGESA (now at v9) for direct inclusion into UEFI
build environments.  Therefore, unlike the previous Arch2008
(a.k.a. v5), it can't be built without additional source, e.g. by
combining with EDK II, and it has no entry points for easily
building it into a legacy BIOS.

AGESA in coreboot now relies on the FSP 2.0 framework published
by Intel and uses the existing fsp2_0 driver.

* Add fsp_memory_init() to romstage.c.  Although Picasso comes out
  of reset with DRAM alive, this call is added to maximize
  compatibility and facilitate internal development.  Future work
  may look at removing it.  AGESA reports the memory map to coreboot
  via HOBs returned from fsp_memory_init().
* AGESA currently sets up MTRRs, as in most older generations.
  Take ownership back immediately before running ramstage.
* Remove cbmem initialization, as the FSP driver handles this.
* Add chipset_handle_reset() for compatibility.
* Top of memory is determined by the FSP driver checking the HOBs
  passed from AGESA.  Note that relying on the TOM register happens
  to be misleading when UMA is below 4GB.

BUG=b:147042464
TEST=Boot trembyle to payload

Change-Id: Iecb3a3f2599a8ccbc168b1d26a0271f51b71dcf0
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34423
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/picasso/memmap.c | 48 ++++++++++++++++----------------------------
 1 file changed, 17 insertions(+), 31 deletions(-)

(limited to 'src/soc/amd/picasso/memmap.c')

diff --git a/src/soc/amd/picasso/memmap.c b/src/soc/amd/picasso/memmap.c
index c6fd11874a..7b504afc75 100644
--- a/src/soc/amd/picasso/memmap.c
+++ b/src/soc/amd/picasso/memmap.c
@@ -6,37 +6,11 @@
 #include <assert.h>
 #include <stdint.h>
 #include <console/console.h>
-#include <cpu/x86/msr.h>
 #include <cpu/x86/smm.h>
 #include <cpu/amd/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <cbmem.h>
-#include <arch/bert_storage.h>
-#include <soc/northbridge.h>
-#include <soc/iomap.h>
-#include <amdblocks/acpimmio.h>
-
-void *cbmem_top_chipset(void)
-{
-	msr_t tom = rdmsr(TOP_MEM);
-
-	if (!tom.lo)
-		return 0;
-
-	/* 8MB alignment to keep MTRR usage low */
-	return (void *)ALIGN_DOWN(restore_top_of_low_cacheable()
-			- CONFIG_SMM_TSEG_SIZE, 8*MiB);
-}
-
-static uintptr_t smm_region_start(void)
-{
-	return (uintptr_t)cbmem_top();
-}
-
-static size_t smm_region_size(void)
-{
-	return CONFIG_SMM_TSEG_SIZE;
-}
+#include <memrange.h>
+#include <fsp/util.h>
+#include <FspGuids.h>
 
 /*
  * For data stored in TSEG, ensure TValid is clear so R/W access can reach
@@ -63,9 +37,21 @@ static void clear_tvalid(void)
 void smm_region(uintptr_t *start, size_t *size)
 {
 	static int once;
+	struct range_entry tseg;
+	int status;
+
+	*start = 0;
+	*size = 0;
+
+	status = fsp_find_range_hob(&tseg, AMD_FSP_TSEG_HOB_GUID.b);
+
+	if (status < 0) {
+		printk(BIOS_ERR, "Error: unable to find TSEG HOB\n");
+		return;
+	}
 
-	*start = smm_region_start();
-	*size = smm_region_size();
+	*start = (uintptr_t)range_entry_base(&tseg);
+	*size = range_entry_size(&tseg);
 
 	if (!once) {
 		clear_tvalid();
-- 
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