From aea59401d053690ce06a5f89be272865e7905682 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 28 May 2021 19:10:13 +0200 Subject: soc/amd/picasso: remove warm reset flag code Since the MCA(X) registers have defined values on the cold boot path, the is_warm_reset check can be dropped. Also the warm reset bit in the NCP_ERR register doesn't behave as the PPR [1] suggested; no matter if something was written to the register or the machine went through a warm reset cycle, the NCP_WARM_BOOT bit never got set. [1] checked with PPR for AMD Family 17h Models 11h,18h B1 (RV,PCO) #55570 Rev 3.15 Signed-off-by: Felix Held Change-Id: I4e6df98ffd5d15ca204c9847a76c19c753726737 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55059 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Marshall Dawson --- src/soc/amd/picasso/mca.c | 58 +++++++++++++++++++++++------------------------ 1 file changed, 28 insertions(+), 30 deletions(-) (limited to 'src/soc/amd/picasso/mca.c') diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c index aab95ca48a..2576f6e0d9 100644 --- a/src/soc/amd/picasso/mca.c +++ b/src/soc/amd/picasso/mca.c @@ -159,36 +159,34 @@ void check_mca(void) cap = rdmsr(IA32_MCG_CAP); num_banks = cap.lo & MCA_BANKS_MASK; - if (is_warm_reset()) { - for (i = 0 ; i < num_banks ; i++) { - mci.sts = rdmsr(MCAX_STATUS_MSR(i)); - if (mci.sts.hi || mci.sts.lo) { - int core = cpuid_ebx(1) >> 24; - - printk(BIOS_WARNING, "#MC Error: core %d, bank %d %s\n", - core, i, - i < ARRAY_SIZE(mca_bank_name) ? mca_bank_name[i] : ""); - - printk(BIOS_WARNING, " MC%d_STATUS = %08x_%08x\n", - i, mci.sts.hi, mci.sts.lo); - mci.addr = rdmsr(MCAX_ADDR_MSR(i)); - printk(BIOS_WARNING, " MC%d_ADDR = %08x_%08x\n", - i, mci.addr.hi, mci.addr.lo); - mci.misc = rdmsr(MCAX_MISC0_MSR(i)); - printk(BIOS_WARNING, " MC%d_MISC = %08x_%08x\n", - i, mci.misc.hi, mci.misc.lo); - mci.ctl = rdmsr(MCAX_CTL_MSR(i)); - printk(BIOS_WARNING, " MC%d_CTL = %08x_%08x\n", - i, mci.ctl.hi, mci.ctl.lo); - mci.cmask = rdmsr(MCA_CTL_MASK_MSR(i)); - printk(BIOS_WARNING, " MC%d_CTL_MASK = %08x_%08x\n", - i, mci.cmask.hi, mci.cmask.lo); - - mci.bank = i; - if (CONFIG(ACPI_BERT) - && mca_valid(mci.sts)) - build_bert_mca_error(&mci); - } + for (i = 0 ; i < num_banks ; i++) { + mci.sts = rdmsr(MCAX_STATUS_MSR(i)); + if (mci.sts.hi || mci.sts.lo) { + int core = cpuid_ebx(1) >> 24; + + printk(BIOS_WARNING, "#MC Error: core %d, bank %d %s\n", + core, i, + i < ARRAY_SIZE(mca_bank_name) ? mca_bank_name[i] : ""); + + printk(BIOS_WARNING, " MC%d_STATUS = %08x_%08x\n", + i, mci.sts.hi, mci.sts.lo); + mci.addr = rdmsr(MCAX_ADDR_MSR(i)); + printk(BIOS_WARNING, " MC%d_ADDR = %08x_%08x\n", + i, mci.addr.hi, mci.addr.lo); + mci.misc = rdmsr(MCAX_MISC0_MSR(i)); + printk(BIOS_WARNING, " MC%d_MISC = %08x_%08x\n", + i, mci.misc.hi, mci.misc.lo); + mci.ctl = rdmsr(MCAX_CTL_MSR(i)); + printk(BIOS_WARNING, " MC%d_CTL = %08x_%08x\n", + i, mci.ctl.hi, mci.ctl.lo); + mci.cmask = rdmsr(MCA_CTL_MASK_MSR(i)); + printk(BIOS_WARNING, " MC%d_CTL_MASK = %08x_%08x\n", + i, mci.cmask.hi, mci.cmask.lo); + + mci.bank = i; + if (CONFIG(ACPI_BERT) + && mca_valid(mci.sts)) + build_bert_mca_error(&mci); } } -- cgit v1.2.3