From 8c1e603800d8403bf16ea6bb247eb7793fc063d0 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Mon, 22 Jun 2020 18:16:39 +0300 Subject: soc/amd/common,picasso: Place some ENV_X86 guards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Base address symbols for ACPIMMIO banks that would not get assigned at runtime must not resolve at linker-stage either. The build of PSP-verstage should pass without the preprocessor macros that have x86-centric view of memory space. Change-Id: I3cb1b5a90023ebc4359835be716c5e3f9451df60 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/42523 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Angel Pons --- src/soc/amd/picasso/include/soc/iomap.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/soc/amd/picasso/include') diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 43e56582a1..0296c87dd8 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -3,6 +3,8 @@ #ifndef AMD_PICASSO_IOMAP_H #define AMD_PICASSO_IOMAP_H +#if ENV_X86 + /* MMIO Ranges */ /* IO_APIC_ADDR defined in arch/x86 0xfec00000 */ #define GNB_IO_APIC_ADDR 0xfec01000 @@ -22,6 +24,8 @@ /* Reserved 0xfecd1000-0xfedc3fff */ +#endif /* ENV_X86 */ + /* * Picasso/Dali have I2C0 and I2C1 wired to the Sensor Fusion Hub (SFH/MP2). * The controllers are not directly accessible via the x86. @@ -37,6 +41,8 @@ #define I2C_MASTER_START_INDEX 2 #define I2C_SLAVE_DEV_COUNT 1 +#if ENV_X86 + #define APU_I2C2_BASE 0xfedc4000 #define APU_I2C3_BASE 0xfedc5000 #define APU_I2C4_BASE 0xfedc6000 @@ -62,6 +68,8 @@ #define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) +#endif /* ENV_X86 */ + /* I/O Ranges */ #define ACPI_SMI_CTL_PORT 0xb2 #define PICASSO_ACPI_IO_BASE CONFIG_PICASSO_ACPI_IO_BASE -- cgit v1.2.3