From 806ea463dbc20c9a577923af51e9976baaf6790a Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Sat, 11 Apr 2020 10:06:37 -0600 Subject: soc/amd/picasso: add sd/emmc0 configuration to chip.h In order to isolate mainboard code from direct FSPS manipulation allow sd/emmc0 configuration to be supplied by devicetree.cb. BUG=b:153502861 Change-Id: I2569ccccd638faaf2c9ac68fe582ecb9fa967d9f Signed-off-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2146439 Commit-Queue: Aaron Durbin Tested-by: Aaron Durbin Reviewed-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40876 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/amd/picasso/include/soc/platform_descriptors.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'src/soc/amd/picasso/include') diff --git a/src/soc/amd/picasso/include/soc/platform_descriptors.h b/src/soc/amd/picasso/include/soc/platform_descriptors.h index bc67550fd0..7a8444b062 100644 --- a/src/soc/amd/picasso/include/soc/platform_descriptors.h +++ b/src/soc/amd/picasso/include/soc/platform_descriptors.h @@ -8,6 +8,21 @@ #include #include +/* These tempory macros apply to emmc0_mode field in FSP_S_CONFIG. + * TODO: Remove when official definitions arrive. */ +#define SD_DISABLE 0 +#define SD_LOW_SPEED 1 +#define SD_HIGH_SPEED 2 +#define SD_UHS_I_SDR_50 3 +#define SD_UHS_I_DDR_50 4 +#define SD_UHS_I_SDR_104 5 +#define EMMC_SDR_26 6 +#define EMMC_SDR_52 7 +#define EMMC_DDR_52 8 +#define EMMC_HS200 9 +#define EMMC_HS400 10 +#define EMMC_HS300 11 + /* Mainboard callback to obtain PCIe and DDI descriptors. */ void mainboard_get_pcie_ddi_descriptors( const picasso_fsp_pcie_descriptor **pcie_descs, size_t *pcie_num, -- cgit v1.2.3