From f56b7842274741503b10b197317eeb28720704be Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Fri, 4 Dec 2020 10:29:56 -0700 Subject: soc/amd/picasso: Rename SD_EMMC_EMMC_DDR_52 to SD_EMMC_EMMC_DDR_104 The number at the end actually means the max MiB/s. So 52 MHz clock @ 8x data width, sampled on each clock edge = 104 MiB/s. According to JEDEC Standard No. 84-B51A (JESD84-B51A), maximum bandwidth & clock frequency for various MMC bus speed modes are (at x8 bus width): MMC_Legacy: 26 MB/s at 26 MHz Single Data Rate (SDR) MMC_HS: 52 MB/s at 52 MHz SDR MMC_DDR52: 104 MB/s at 52 MHz Dual Data Rate (DDR) MMC_HS200: 200 MB/s at 200 MHz SDR MMC_HS400: 400 MB/s at 200 MHz DDR BUG=b:159823235 BRANCH=zork TEST=build zork Signed-off-by: Raul E Rangel Change-Id: I7818d8cb5ed5974c60a900477a0aa2ecc904db0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/48309 Reviewed-by: Jason Glenesk Reviewed-by: Marshall Dawson Reviewed-by: Rob Barnes Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/fsp_params.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc/amd/picasso/fsp_params.c') diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c index a08a209bc1..c7befe43dd 100644 --- a/src/soc/amd/picasso/fsp_params.c +++ b/src/soc/amd/picasso/fsp_params.c @@ -38,8 +38,8 @@ static void fsps_update_emmc_config(FSP_S_CONFIG *scfg, case SD_EMMC_EMMC_SDR_52: val = EMMC_SDR_52; break; - case SD_EMMC_EMMC_DDR_52: - val = EMMC_DDR_52; + case SD_EMMC_EMMC_DDR_104: + val = EMMC_DDR_104; break; case SD_EMMC_EMMC_HS200: val = EMMC_HS200; -- cgit v1.2.3