From 4e80fae2367d3a0a64ac2896dc654e0cf842fc4e Mon Sep 17 00:00:00 2001
From: Raul E Rangel <rrangel@chromium.org>
Date: Wed, 16 Dec 2020 10:08:41 -0700
Subject: soc/amd/picasso: Correctly populate the PCI interrupt line register

The PCI interrupt line registers are used as a last resort if routing
can't be fetched from either ACPI or the MPTable. This change correctly
sets the registers. It overrides the pirq_data set by the mainboards
since the routing is fixed in AGESA.

BUG=b:170595019
TEST=Boot ezkinil with `pci=nomsi,noacpi amd_iommu=off noapic`
Verified all PCI peripherals are still functional.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If5d4d8f613c8d0fa9b43cefa804824681c3410d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/soc/amd/picasso/fch.c | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'src/soc/amd/picasso/fch.c')

diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c
index d5278cbd0f..4c8c584cbf 100644
--- a/src/soc/amd/picasso/fch.c
+++ b/src/soc/amd/picasso/fch.c
@@ -22,6 +22,7 @@
 #include <soc/southbridge.h>
 #include <soc/smi.h>
 #include <soc/amd_pci_int_defs.h>
+#include <soc/pci.h>
 #include <soc/pci_devs.h>
 #include <soc/nvs.h>
 #include <types.h>
@@ -259,6 +260,9 @@ static void set_pci_irqs(void *unused)
 	/* Write PCI_INTR regs 0xC00/0xC01 */
 	write_pci_int_table();
 
+	/* pirq_data is consumed by `write_pci_cfg_irqs` */
+	populate_pirq_data();
+
 	/* Write IRQs for all devicetree enabled devices */
 	write_pci_cfg_irqs();
 }
-- 
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