From e2497d0181f5ab20d012c761400601b15565ce58 Mon Sep 17 00:00:00 2001 From: Chris Wang Date: Mon, 3 Aug 2020 22:36:13 +0800 Subject: mb/google/zork: keep the c-state IO base address alignment Align the C-state MSR value of BSP with AGESA. BUG=b:162705221 BRANCH=none TEST=Check the MSR value is correct and BSP can enter CC6 with AVT tool Signed-off-by: Chris Wang Change-Id: Ib98d34af518439d338326446c20601867ad31690 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44135 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/amd/picasso/cpu.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src/soc/amd/picasso/cpu.c') diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index c42f400362..4d6e98d221 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -46,6 +46,15 @@ int get_cpu_count(void) return 1 + (cpuid_ecx(0x80000008) & 0xff); } +static void set_cstate_io_addr(void) +{ + msr_t cst_addr; + + cst_addr.hi = 0; + cst_addr.lo = ACPI_CPU_CONTROL; + wrmsr(MSR_CSTATE_ADDRESS, cst_addr); +} + static void fill_in_relocation_params(struct smm_relocation_params *params) { uintptr_t tseg_base; @@ -109,6 +118,7 @@ static void model_17_init(struct device *dev) { check_mca(); setup_lapic(); + set_cstate_io_addr(); amd_update_microcode_from_cbfs(); } -- cgit v1.2.3