From 41a5954a6785bfad95dce36611b92f1123e350e2 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Tue, 19 Dec 2023 22:33:46 +0100
Subject: soc/amd/picasso/acpi: move SoC-common code from dsdt.asl to soc.asl

To avoid code duplication and to also bring the mainboards using the
Picasso SoC more in line with Cezanne and newer, factor out the SoC-
specific code from the mainboard's dsdt.asl files to the SoC's soc.asl.

TEST=Timeless builds result in identical images for Bilby, Mandolin, and
Zork/Morphius

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id4ed3a3d3cb55c8b3b474c66a7c1700e24fe908e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
---
 src/soc/amd/picasso/acpi/soc.asl | 55 ++++++++++++++++++++++++++--------------
 1 file changed, 36 insertions(+), 19 deletions(-)

(limited to 'src/soc/amd/picasso/acpi/soc.asl')

diff --git a/src/soc/amd/picasso/acpi/soc.asl b/src/soc/amd/picasso/acpi/soc.asl
index a958570905..7c13f0863e 100644
--- a/src/soc/amd/picasso/acpi/soc.asl
+++ b/src/soc/amd/picasso/acpi/soc.asl
@@ -1,30 +1,47 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <soc/amd/common/acpi/pci_root.asl>
+#include "globalnvs.asl"
 
-ROOT_BRIDGE(PCI0)
+/* Power state notification to ALIB */
+#include "pnot.asl"
 
-Scope(PCI0) {
-	/* Describe the AMD Northbridge */
-	#include "northbridge.asl"
+/* Contains the supported sleep states for this chipset */
+#include <soc/amd/common/acpi/sleepstates.asl>
 
-	/* Describe the AMD Fusion Controller Hub */
-	#include <soc/amd/common/acpi/lpc.asl>
-	#include <soc/amd/common/acpi/platform.asl>
-}
+/* Contains _SWS methods */
+#include <soc/amd/common/acpi/acpi_wake_source.asl>
 
-/* PCI IRQ mapping for the Southbridge */
-#include "pci_int_defs.asl"
+/* System Bus */
+Scope(\_SB) { /* Start \_SB scope */
+	/* global utility methods expected within the \_SB scope */
+	#include <arch/x86/acpi/globutil.asl>
 
-/* Describe PCI INT[A-H] for the Southbridge */
-#include <soc/amd/common/acpi/pci_int.asl>
+	ROOT_BRIDGE(PCI0)
 
-/* Describe the MMIO devices in the FCH */
-#include "mmio.asl"
+	Scope(PCI0) {
+		/* Describe the AMD Northbridge */
+		#include "northbridge.asl"
 
-/* Add GPIO library */
-#include <soc/amd/common/acpi/gpio_bank_lib.asl>
+		/* Describe the AMD Fusion Controller Hub */
+		#include <soc/amd/common/acpi/lpc.asl>
+		#include <soc/amd/common/acpi/platform.asl>
+	}
 
-#if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)
-#include <soc/amd/common/acpi/dptc.asl>
-#endif
+	/* PCI IRQ mapping for the Southbridge */
+	#include "pci_int_defs.asl"
+
+	/* Describe PCI INT[A-H] for the Southbridge */
+	#include <soc/amd/common/acpi/pci_int.asl>
+
+	/* Describe the MMIO devices in the FCH */
+	#include "mmio.asl"
+
+	/* Add GPIO library */
+	#include <soc/amd/common/acpi/gpio_bank_lib.asl>
+
+	#if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)
+	#include <soc/amd/common/acpi/dptc.asl>
+	#endif
+
+} /* End \_SB scope */
-- 
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