From 778c8a77c1fc468b320f3471e7e753fd6f4afed7 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Mon, 22 Apr 2019 16:14:12 -0600 Subject: soc/amd/picasso: Stub out bootblock Remove all Picasso bootblock support. CAR is not a supportable feature, and the first code executed at the reset vector will be a hybrid romstage. Details for this implementation may be found in Documentation/soc/amd/picasso/family17h.md. TEST=None BUG=b:130804851 Signed-off-by: Martin Roth Change-Id: I8edf45c02dc5bfcdca03abf1294db4be508682cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/32413 Tested-by: build bot (Jenkins) Reviewed-by: Richard Spiegel Reviewed-by: Edward O'Callaghan Reviewed-by: HAOUAS Elyes --- src/soc/amd/picasso/Makefile.inc | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) (limited to 'src/soc/amd/picasso/Makefile.inc') diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index bb24c67b05..e8c022fcda 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -37,17 +37,12 @@ subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/pae subdirs-y += ../../../cpu/x86/smm -bootblock-$(CONFIG_STONEYRIDGE_UART) += uart.c +# TODO: Make coreboot modifications so bootblock can be removed. This soc +# also selects C_ENVIRONMENT_BOOTBLOCK to enforce certain codepaths +# in romstage. As a result, the bootblock build also needs a +# dummy cache_as_ram.S +bootblock-y += cache_as_ram.S bootblock-y += bootblock/bootblock.c -bootblock-y += gpio.c -bootblock-y += i2c.c -bootblock-y += monotonic_timer.c -bootblock-y += pmutil.c -bootblock-y += reset.c -bootblock-y += tsc_freq.c -bootblock-y += southbridge.c -bootblock-$(CONFIG_SPI_FLASH) += spi.c -bootblock-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c romstage-y += i2c.c romstage-y += romstage.c -- cgit v1.2.3