From 4064677fde9fe57c672fd16563e674d38a1b94eb Mon Sep 17 00:00:00 2001 From: Fred Reitberger Date: Wed, 8 Feb 2023 13:05:05 -0500 Subject: soc/amd/phoenix: Expand APOB to 256K APOB on Phoenix is larger, so expand the reserved DRAM and MRC_CACHE regions to fit. This requires moving memory addresses around to prevent overlapping memory linker errors. TEST='./util/scripts/testsoc -K PHOENIX -K GLINDA' successfully builds all boards Signed-off-by: Fred Reitberger Change-Id: I42af7230ca5f09ba66b2b3c4f99ac3feac7feeea Reviewed-on: https://review.coreboot.org/c/coreboot/+/72905 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/soc/amd/phoenix/Kconfig | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'src/soc/amd/phoenix/Kconfig') diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig index 03cf8366ff..b108c8f2da 100644 --- a/src/soc/amd/phoenix/Kconfig +++ b/src/soc/amd/phoenix/Kconfig @@ -116,11 +116,11 @@ config PSP_APOB_DRAM_ADDRESS config PSP_APOB_DRAM_SIZE hex - default 0x1E000 + default 0x40000 config PSP_SHAREDMEM_BASE hex - default 0x201F000 if VBOOT + default 0x2041000 if VBOOT default 0x0 help This variable defines the base address in DRAM memory where PSP copies @@ -165,7 +165,7 @@ config C_ENV_BOOTBLOCK_SIZE config ROMSTAGE_ADDR hex - default 0x2040000 + default 0x2060000 help Sets the address in DRAM where romstage should be loaded. @@ -177,7 +177,7 @@ config ROMSTAGE_SIZE config FSP_M_ADDR hex - default 0x20C0000 + default 0x20E0000 help Sets the address in DRAM where FSP-M should be loaded. cbfstool performs relocation of FSP-M to this address. @@ -197,7 +197,7 @@ config FSP_TEMP_RAM_SIZE config VERSTAGE_ADDR hex depends on VBOOT_SEPARATE_VERSTAGE - default 0x2180000 + default 0x21A0000 help Sets the address in DRAM where verstage should be loaded if running as a separate stage on x86. -- cgit v1.2.3