From e3adefedca3d35a576c87ff8584dacc61f5587b1 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 19 Jan 2023 17:04:47 +0100 Subject: soc/amd/mendocino/acpi: remove RTC wake workaround Commit 78ee4889dc32 ("soc/amd/cezanne/acpi: Add support for RTC workaround") added a workaround for the Cezanne silicon. This was copied to the Mendocino code, but from both the discussion in b:209705576 and the referenced amd_pmc_verify_czn_rtc function in drivers/platform/x86/ amd/pmc.c that is only called if pdev->cpu_id == AMD_CPU_ID_CZN is true Mendocino doesn't need that workaround, so remove it. TEST=Running suspend_stress_test -c 5 on Chausie shows no errors Signed-off-by: Felix Held Change-Id: I7d0b35ef8cf88ff0b9bed8820b8da32c2058cc1b Reviewed-on: https://review.coreboot.org/c/coreboot/+/72091 Reviewed-by: Matt DeVillier Reviewed-by: Raul Rangel Reviewed-by: Fred Reitberger Tested-by: build bot (Jenkins) --- src/soc/amd/mendocino/acpi/rtc_workaround.asl | 28 --------------------------- src/soc/amd/mendocino/acpi/soc.asl | 2 -- 2 files changed, 30 deletions(-) delete mode 100644 src/soc/amd/mendocino/acpi/rtc_workaround.asl (limited to 'src/soc/amd/mendocino') diff --git a/src/soc/amd/mendocino/acpi/rtc_workaround.asl b/src/soc/amd/mendocino/acpi/rtc_workaround.asl deleted file mode 100644 index 8bbca4e3f1..0000000000 --- a/src/soc/amd/mendocino/acpi/rtc_workaround.asl +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* TODO: Check if this is still correct */ - -/* - * Workaround for RTC on Cezanne. - * See https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/kernel/v5.10/drivers/platform/x86/amd-pmc.c;l=416;drc=54a96af06ae6851e4a02e8dd700de0d579ef7839 - */ - -Scope (\_SB.PEP) { - Name (_PRW, Package () { - Package() {\_SB.GPIO, 0}, - 0x03 - }) -} - -Scope (\_SB.GPIO) { - Name (_AEI, ResourceTemplate () { - GpioInt(Edge, ActiveHigh, ExclusiveAndWake, PullNone, 0x0000, "\\_SB.GPIO",,,,) - { - 44 /* int_shdwsysalarmfire */ - } - }) - - Method (_E2C, 0, Serialized) { - Notify (\_SB_.PEP, 0x02) - } -} diff --git a/src/soc/amd/mendocino/acpi/soc.asl b/src/soc/amd/mendocino/acpi/soc.asl index 5af6d8c533..7e9e2e8cc2 100644 --- a/src/soc/amd/mendocino/acpi/soc.asl +++ b/src/soc/amd/mendocino/acpi/soc.asl @@ -33,8 +33,6 @@ Scope(\_SB) { #include #endif -#include "rtc_workaround.asl" - /* Enable DPTC interface with AMD ALIB */ External(\_SB.DPTC, MethodObj) -- cgit v1.2.3