From cbe55a1728e4f5f3c46e92754fb098aab85fbe91 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 3 Mar 2023 22:37:34 +0100 Subject: soc/amd: rename ACPI_CPU_CONTROL to ACPI_CSTATE_CONTROL for non-CAR CPUs The legacy ACPI CPU control registers in IO space where the first 4 IO locations control the CPU throttling value don't exist any more on the Zen-based CPUs. Instead this IO address is written to MSR_CSTATE_ADDRESS in set_cstate_io_addr which will cause accesses from the 8 IO addresses beginning with ACPI_CSTATE_CONTROL to be trapped in the CPU core. Reads from those IO addresses will cause the CPU to enter low C states. Signed-off-by: Felix Held Change-Id: I2c34e201cc0add1026edd7a97c70aa57f057782b Reviewed-on: https://review.coreboot.org/c/coreboot/+/73427 Tested-by: build bot (Jenkins) Reviewed-by: Fred Reitberger --- src/soc/amd/mendocino/include/soc/iomap.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/amd/mendocino') diff --git a/src/soc/amd/mendocino/include/soc/iomap.h b/src/soc/amd/mendocino/include/soc/iomap.h index 630940bb3f..1e1120cfbe 100644 --- a/src/soc/amd/mendocino/include/soc/iomap.h +++ b/src/soc/amd/mendocino/include/soc/iomap.h @@ -48,7 +48,7 @@ #define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) #define ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04) #define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x08) -#define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x10) +#define ACPI_CSTATE_CONTROL (ACPI_IO_BASE + 0x10) #define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20) #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) #define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) -- cgit v1.2.3