From 665476df2bf16c84ccf7037bde67d76cc0604673 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 3 Aug 2022 22:18:18 +0200 Subject: soc/amd/mendocino: enable CPPC feature This is sort-of reverts commit cbf290c692b2 ("soc/amd/sabrina: drop CPPC code"), since it turned out that the CPPC feature is supported on Sabrina (now Mendocino) despite this being missing from the documentation I looked at when writing the patch referenced above. Since the CPPC ACPI code generation functionality has been moved to common code, this isn't a direct revert. BUG=b:237336330 TEST=None Signed-off-by: Felix Held Change-Id: I1c059653eeae207d723c77e8a78b19c86e362296 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66401 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian --- src/soc/amd/mendocino/Kconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/soc/amd/mendocino/Kconfig') diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig index 86ce2cc8bb..e9d549d0ce 100644 --- a/src/soc/amd/mendocino/Kconfig +++ b/src/soc/amd/mendocino/Kconfig @@ -53,6 +53,7 @@ config SOC_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_ACPI # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_ACPI_ALIB # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_ACPI_CPPC select SOC_AMD_COMMON_BLOCK_ACPI_GPIO select SOC_AMD_COMMON_BLOCK_ACPI_IVRS # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_AOAC @@ -82,6 +83,7 @@ config SOC_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_UART select SOC_AMD_COMMON_BLOCK_UCODE + select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB select SOC_AMD_COMMON_FSP_DMI_TABLES # TODO: Check if this is still correct select SOC_AMD_COMMON_FSP_PCI # TODO: Check if this is still correct select SSE2 -- cgit v1.2.3