From db96c9634ee32278cf0f0b64e34d149de2b03298 Mon Sep 17 00:00:00 2001 From: Maximilian Brune Date: Fri, 9 Aug 2024 14:47:19 +0200 Subject: soc/amd/glinda: Update SCI mapping source: PPR #57254 Rev 1.71 Change-Id: I5eaed888109b89c25bcf0ba91abefa7c36c1851b Signed-off-by: Maximilian Brune Reviewed-on: https://review.coreboot.org/c/coreboot/+/84381 Reviewed-by: Marshall Dawson Tested-by: build bot (Jenkins) --- src/soc/amd/glinda/include/soc/pci_devs.h | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) (limited to 'src/soc/amd/glinda/include') diff --git a/src/soc/amd/glinda/include/soc/pci_devs.h b/src/soc/amd/glinda/include/soc/pci_devs.h index a37d3eeb14..e85a6e3372 100644 --- a/src/soc/amd/glinda/include/soc/pci_devs.h +++ b/src/soc/amd/glinda/include/soc/pci_devs.h @@ -65,10 +65,6 @@ #define GFX_HDA_FUNC 1 #define GFX_HDA_DEVFN PCI_DEVFN(GFX_HDA_DEV, GFX_HDA_FUNC) -#define XHCI0_DEV 0x0 -#define XHCI0_FUNC 3 -#define XHCI0_DEVFN PCI_DEVFN(XHCI0_DEV, XHCI0_FUNC) - #define XHCI1_DEV 0x0 #define XHCI1_FUNC 4 #define XHCI1_DEVFN PCI_DEVFN(XHCI1_DEV, XHCI1_FUNC) @@ -89,9 +85,18 @@ #define PCIE_ABC_C_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) #define SOC_PCIE_GPP_C_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) -#define XHCI2_DEV 0x0 -#define XHCI2_FUNC 0 -#define XHCI2_DEVFN PCI_DEVFN(XHCI2_DEV, XHCI2_FUNC) +#define XHCI0_DEV 0x0 +#define XHCI0_FUNC 0 +#define XHCI0_DEVFN PCI_DEVFN(XHCI0_DEV, XHCI0_FUNC) + +#define USB4_XHCI0_DEV 0x0 +#define USB4_XHCI0_FUNC 3 +#define USB4_XHCI0_DEVFN PCI_DEVFN(USB4_XHCI0_DEV, USB4_XHCI0_FUNC) + +#define USB4_XHCI1_DEV 0x0 +#define USB4_XHCI1_FUNC 4 +#define USB4_XHCI1_DEVFN PCI_DEVFN(USB4_XHCI1_DEV, USB4_XHCI1_FUNC) + /* SMBUS */ #define SMBUS_DEV 0x14 -- cgit v1.2.3