From f95a11eff5217a396dc43288f0c547559b5d221a Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Fri, 21 Oct 2022 16:43:08 -0600
Subject: soc/amd: Add framework for Glinda SoC

This adds the initial framework for the Glinda SoC, based on what's been
done for Morgana already.

I believe that there's more that can be made common, but that work will
continue as both platforms are developed.

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: I43d0fdb711c441dc410a14f6bb04b808abefe920
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
---
 src/soc/amd/glinda/chip.c | 64 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 64 insertions(+)
 create mode 100644 src/soc/amd/glinda/chip.c

(limited to 'src/soc/amd/glinda/chip.c')

diff --git a/src/soc/amd/glinda/chip.c b/src/soc/amd/glinda/chip.c
new file mode 100644
index 0000000000..b0b90ee8ad
--- /dev/null
+++ b/src/soc/amd/glinda/chip.c
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* TODO: Update for Glinda */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <fsp/api.h>
+#include <soc/acpi.h>
+#include <soc/cpu.h>
+#include <soc/data_fabric.h>
+#include <soc/pci_devs.h>
+#include <soc/southbridge.h>
+#include <types.h>
+#include "chip.h"
+
+struct device_operations glinda_cpu_bus_ops = {
+	.read_resources	= noop_read_resources,
+	.set_resources	= noop_set_resources,
+	.init		= mp_cpu_bus_init,
+	.acpi_fill_ssdt	= generate_cpu_entries,
+};
+
+static const char *soc_acpi_name(const struct device *dev)
+{
+	if (dev->path.type == DEVICE_PATH_DOMAIN)
+		return "PCI0";
+
+	if (dev->path.type != DEVICE_PATH_PCI)
+		return NULL;
+
+	printk(BIOS_WARNING, "Unknown PCI device: dev: %d, fn: %d\n",
+	       PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn));
+	return NULL;
+};
+
+struct device_operations glinda_pci_domain_ops = {
+	.read_resources	= pci_domain_read_resources,
+	.set_resources	= pci_domain_set_resources,
+	.scan_bus	= pci_domain_scan_bus,
+	.acpi_name	= soc_acpi_name,
+};
+
+static void soc_init(void *chip_info)
+{
+	default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables;
+
+	fsp_silicon_init();
+
+	data_fabric_set_mmio_np();
+
+	fch_init(chip_info);
+}
+
+static void soc_final(void *chip_info)
+{
+	fch_final(chip_info);
+}
+
+struct chip_operations soc_amd_glinda_ops = {
+	CHIP_NAME("AMD Glinda SoC")
+	.init = soc_init,
+	.final = soc_final
+};
-- 
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