From e5592d3d99af72be58d8392d7957be8cd9632e7c Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 4 Feb 2022 13:59:29 +0100 Subject: soc/amd/common/block/acpimmio/print_reset_status: extend bit name table Bit 23 in the PM_RST_STATUS register is called LtReset on Stoneyridge and ShutdownMsg on Picasso/Cezanne/Sabrina. Bit 30 is reserved on Stoneyridge and defined as SdpParityErr on the newer SoCs. Bit 31 is only defined for Sabrina. Since the default value of undefined bits is 0 it isn't a problem to have descriptions for reserved reset status bits on some SoCs. Signed-off-by: Felix Held Change-Id: I0782116d327fcad3817a10eb237ac6c8294846b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61624 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/soc/amd/common/block/acpimmio/print_reset_status.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/soc/amd/common') diff --git a/src/soc/amd/common/block/acpimmio/print_reset_status.c b/src/soc/amd/common/block/acpimmio/print_reset_status.c index 309401e420..5ff04125e3 100644 --- a/src/soc/amd/common/block/acpimmio/print_reset_status.c +++ b/src/soc/amd/common/block/acpimmio/print_reset_status.c @@ -41,13 +41,15 @@ void fch_print_pmxc0_status(void) [20] = "DoFullReset", [21] = "SleepReset", [22] = "KbReset", - [23] = "LtReset", + [23] = "LtReset/ShutdownMsg", [24] = "FailBootRst", [25] = "WatchdogIssueReset", [26] = "RemoteResetFromASF", [27] = "SyncFlood", [28] = "HangReset", [29] = "EcWatchdogRst", + [30] = "SdpParityErr", + [31] = "SwSyncFloodFlag", }; printk(BIOS_DEBUG, "PMxC0 STATUS: 0x%x ", pmxc0_status); -- cgit v1.2.3