From b84c6167505ca76239b8bd59f4ebb3c115111de5 Mon Sep 17 00:00:00 2001 From: Michał Żygowski Date: Mon, 23 Mar 2020 14:41:32 +0100 Subject: amd/common/acpi: move thermal zone to common location MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski Change-Id: I048d1906bc474be4d5a4e44b9c7ae28f53b49d5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39779 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Nico Huber Reviewed-by: Christian Walter Reviewed-by: Angel Pons --- src/soc/amd/common/acpi/thermal_zone.asl | 92 ++++++++++++++++++++++++++++++++ 1 file changed, 92 insertions(+) create mode 100644 src/soc/amd/common/acpi/thermal_zone.asl (limited to 'src/soc/amd/common') diff --git a/src/soc/amd/common/acpi/thermal_zone.asl b/src/soc/amd/common/acpi/thermal_zone.asl new file mode 100644 index 0000000000..e6ab43235b --- /dev/null +++ b/src/soc/amd/common/acpi/thermal_zone.asl @@ -0,0 +1,92 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Include this file into a mainboard DSDT inside the PCI device + * "Northbridge Miscellaneous Control (Northbridge function 3)" and it + * will expose the temperature sensor of the processor as a thermal + * zone. + * + * Families 10 through 14 and some family 15 CPUs are supported. + * + * If, for example, the NB Misc. Control device is on 0:18.3, include + * the following: + * + * Scope (\_SB.PCI0) { + * Device (K10M) { + * Name (_ADR, 0x00180003) + * #include + * } + * } + * + * Do not include this if the board is affected by erratum 319 as the + * thermal sensor of Socket F/AM2+ processors may be unreliable. + * (Erratum 319 affects AM2+ boards, AM3 and later should be fine) + */ + +#ifndef K10TEMP_HOT_OFFSET +# define K10TEMP_HOT_OFFSET 50 +#endif + +#define K10TEMP_KELVIN_OFFSET 2732 +#define K10TEMP_TLIMIT_OFFSET 520 + +OperationRegion (TCFG, PCI_Config, 0x64, 0x4) +Field (TCFG, ByteAcc, NoLock, Preserve) { + HTCE, 1, /* Hardware thermal control enable */ + , 15, + TLMT, 7, /* (LimitTmp - 52) / 0.5 */ + , 9, +} + +OperationRegion (TCTL, PCI_Config, 0xa4, 0x4) +Field (TCTL, ByteAcc, NoLock, Preserve) { + , 21, + TNOW, 11, /* CurTmp / 0.125 */ +} + +ThermalZone (TZ00) { + Name (_STR, Unicode ("AMD CPU Core Thermal Sensor")) + + Method (_STA) { + If (LEqual (HTCE, One)) { + Return (0x0F) + } + Return (Zero) + } + + Method (_TMP) { /* Current temp in tenths degree Kelvin. */ + Multiply (TNOW, 10, Local0) + ShiftRight (Local0, 3, Local0) + Return (Add (Local0, K10TEMP_KELVIN_OFFSET)) + } + + /* + * TLMT indicates threshold where HTC become active. That is the processor will limit + * P-State and power consumption in order to cool down. + */ + Method (_PSV) { /* Passive temp in tenths degree Kelvin. */ + Multiply (TLMT, 10, Local0) + ShiftRight (Local0, 1, Local0) + Add (Local0, K10TEMP_TLIMIT_OFFSET, Local0) + Return (Add (Local0, K10TEMP_KELVIN_OFFSET)) + } + + Method (_HOT) { /* Hot temp in tenths degree Kelvin. */ + Return (Add (_PSV, K10TEMP_HOT_OFFSET)) + } + + Method (_CRT) { /* Critical temp in tenths degree Kelvin. */ + Return (Add (_HOT, K10TEMP_HOT_OFFSET)) + } +} -- cgit v1.2.3