From 1a973434c57fb11478c37ac9fb0b72b4ff0c919c Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Mon, 8 Feb 2021 23:38:25 +0100
Subject: soc/amd: Move soc_route_sci to common/blocks/smi/smi_util
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Change-Id: Ic379723c0bf6e5edf5f3d63cc11b24d0e59b5075
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42988
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/common/block/smi/smi_util.c | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'src/soc/amd/common')

diff --git a/src/soc/amd/common/block/smi/smi_util.c b/src/soc/amd/common/block/smi/smi_util.c
index 19a4e32e30..dcf0c84b0a 100644
--- a/src/soc/amd/common/block/smi/smi_util.c
+++ b/src/soc/amd/common/block/smi/smi_util.c
@@ -56,6 +56,11 @@ void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level)
 	smi_write32(SMI_REG_SMITRIG0, reg32);
 }
 
+void soc_route_sci(uint8_t event)
+{
+	smi_write8(SMI_SCI_MAP(event), event);
+}
+
 /**
  * Configure generation of SCIs.
  */
-- 
cgit v1.2.3