From 199b10fc21ee094af88abb2b5856502565c40ae7 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Sat, 13 Aug 2022 00:29:23 +0200 Subject: soc/amd: rework SPI flash MMIO region handling Only 16 MByte of the SPI flash can be mapped right below the 4 GB boundary. In case of a larger SPI flash size, still only the 16 MByte region starting at 0xff000000 can be configured as WRPROT and be reserved for the MMIO mapped SPI flash region. The next 16 MByte MMIO region starting at address 0xfe000000 contain for example the LAPIC MMIO region, the ACPIMMIO region and the UART/I2C controller MMIO regions which shouldn't be configured as WRPROT. Reserving this region for the MMIO mapped SPI flash would also result in an overlap with the MMIO resources mentioned above. In the case of a smaller SPI flash, reserving the full 16 MByte flash MMIO region makes sure that the resource allocator won't try to put anything else in the lower parts of the 16 MByte SPI mapping region. To avoid the issues described above, always reserve/cache the maximum amount of 16 MBytes of flash that can be mapped below 4 GB. TEST=On boards with 16 MByte SPI flash chips, the resulting image of a timeless build doesn't change with this patch. Verified this on Chausie (Mendocino), Majolica (Cezanne), Cereme (Picasso) and Google/Careena (Stoneyridge). On Mandolin (Picasso) with an 8 MByte flash, the resulting image of a timeless build is different, but neither the coreboot console output nor the Linux dmesg output shows any errors that might be related to this change. Signed-off-by: Felix Held Change-Id: Ie12bd48e48e267a84dc494f67e8e0c7a4a01a320 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66700 Reviewed-by: Martin Roth Reviewed-by: Raul Rangel Reviewed-by: Fred Reitberger Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/cpu/noncar/early_cache.c | 6 ++++-- src/soc/amd/common/block/include/amdblocks/iomap.h | 15 +++++++++++++++ src/soc/amd/common/block/lpc/lpc.c | 6 ++++-- 3 files changed, 23 insertions(+), 4 deletions(-) create mode 100644 src/soc/amd/common/block/include/amdblocks/iomap.h (limited to 'src/soc/amd/common') diff --git a/src/soc/amd/common/block/cpu/noncar/early_cache.c b/src/soc/amd/common/block/cpu/noncar/early_cache.c index d8684eea4d..4bba172ed0 100644 --- a/src/soc/amd/common/block/cpu/noncar/early_cache.c +++ b/src/soc/amd/common/block/cpu/noncar/early_cache.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include @@ -61,8 +62,9 @@ void early_cache_setup(void) wrmsr(SYSCFG_MSR, sys_cfg); var_mtrr_set(&mtrr_ctx.ctx, 0, ALIGN_DOWN(top_mem.lo, 8 * MiB), MTRR_TYPE_WRBACK); - /* TODO: check if we should always mark 16 MByte below 4 GByte as WRPROT */ - var_mtrr_set(&mtrr_ctx.ctx, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); + /* Always mark the 16 MByte right below the 4 GB boundary as WRPROT */ + var_mtrr_set(&mtrr_ctx.ctx, FLASH_BELOW_4GB_MAPPING_REGION_BASE, + FLASH_BELOW_4GB_MAPPING_REGION_SIZE, MTRR_TYPE_WRPROT); commit_mtrr_setup(&mtrr_ctx.ctx); diff --git a/src/soc/amd/common/block/include/amdblocks/iomap.h b/src/soc/amd/common/block/include/amdblocks/iomap.h new file mode 100644 index 0000000000..759466b052 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/iomap.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_BLOCK_IOMAP_H +#define AMD_BLOCK_IOMAP_H + +/* + * A maximum of 16 MBytes of the SPI flash can be mapped right below the 4 GB boundary. For + * region reservation and cacheability configuration purposes, we can use this maximum value + * and don't need to make this dependent on the flash size. This also makes sure that in case + * of flash sizes above 16 MByte the MMIO region right below won't get configured wrongly. + */ +#define FLASH_BELOW_4GB_MAPPING_REGION_BASE ((0xffffffff - 16 * MiB) + 1) +#define FLASH_BELOW_4GB_MAPPING_REGION_SIZE (16 * MiB) + +#endif /* AMD_BLOCK_IOMAP_H */ diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index c02f2978cd..3d1b2d44fc 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -109,9 +110,10 @@ static void lpc_read_resources(struct device *dev) res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + /* Only up to 16 MByte of the SPI flash can be mapped right below 4 GB */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->base = FLASH_BASE_ADDR; - res->size = CONFIG_ROM_SIZE; + res->base = FLASH_BELOW_4GB_MAPPING_REGION_BASE; + res->size = FLASH_BELOW_4GB_MAPPING_REGION_SIZE; res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; -- cgit v1.2.3