From 1786601b524f380ebd72bc63083e7e97a8996198 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 24 Mar 2023 20:43:09 +0100 Subject: soc/amd/common/block/cpu/tsc/Makefile: order targets by stage Now that only one build target per stage is included in the build depending on CONFIG_SOC_AMD_COMMON_BLOCK_TSC being set, don't use a separate ifeq block for this. Signed-off-by: Felix Held Change-Id: Id9e551b37707081eb2ea1d682013f57c7ca8aabd Reviewed-on: https://review.coreboot.org/c/coreboot/+/74017 Reviewed-by: Martin Roth Reviewed-by: Fred Reitberger Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/cpu/tsc/Makefile.inc | 19 +++++-------------- 1 file changed, 5 insertions(+), 14 deletions(-) (limited to 'src/soc/amd/common') diff --git a/src/soc/amd/common/block/cpu/tsc/Makefile.inc b/src/soc/amd/common/block/cpu/tsc/Makefile.inc index ade49707ca..65e849a36e 100644 --- a/src/soc/amd/common/block/cpu/tsc/Makefile.inc +++ b/src/soc/amd/common/block/cpu/tsc/Makefile.inc @@ -3,33 +3,24 @@ bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c +bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_TSC) += tsc_freq.c verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c +verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_TSC) += tsc_freq.c romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c +romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_TSC) += tsc_freq.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_TSC) += tsc_freq.c smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c - -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_TSC),y) - -bootblock-y += tsc_freq.c - -verstage_x86-y += tsc_freq.c - -romstage-y += tsc_freq.c - -ramstage-y += tsc_freq.c - -smm-y += tsc_freq.c - -endif # CONFIG_SOC_AMD_COMMON_BLOCK_TSC +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_TSC) += tsc_freq.c -- cgit v1.2.3