From 026caf5def38df8cc2dca0e1acd7adc063e03951 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Sat, 29 Apr 2023 01:59:31 +0200 Subject: soc/amd/common/block/lpc/lpc: increase size of SPI BAR to 4kByte The memory map granularity for those devices is 4kByte. Signed-off-by: Felix Held Change-Id: I8806128bdce8988f5cd7c8fa8a342fdb01eb7f42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74844 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier Reviewed-by: Arthur Heymans --- src/soc/amd/common/block/lpc/lpc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/amd/common') diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index b8fb923c72..5b836eac7b 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -121,7 +121,7 @@ static void lpc_read_resources(struct device *dev) FLASH_BELOW_4GB_MAPPING_REGION_SIZE); /* Add a memory resource for the SPI BAR. */ - mmio_range(dev, 2, SPI_BASE_ADDRESS, 1 * KiB); + mmio_range(dev, 2, SPI_BASE_ADDRESS, 4 * KiB); res = new_resource(dev, 3); /* IOAPIC */ res->base = IO_APIC_ADDR; -- cgit v1.2.3