From eede5a24959139639a0156ccb3795d1468e996bc Mon Sep 17 00:00:00 2001 From: Chris Wang Date: Mon, 20 Feb 2023 09:43:38 +0800 Subject: soc/amd/mendocino: Add new 'STT_ALPHA_APU' parameter for DPTC support Add a new parameter STT_ALPHA_APU' for each DPTC mode. BUG=b:257149501 BRANCH=None TEST=Check if the STT value matches the expected setting. Change-Id: Ib27572712d57585f66030d9e927896a8249e97a7 Signed-off-by: Chris Wang Reviewed-on: https://review.coreboot.org/c/coreboot/+/73123 Tested-by: build bot (Jenkins) Reviewed-by: Tim Van Patten Reviewed-by: Frank Wu Reviewed-by: John Su --- src/soc/amd/common/block/include/amdblocks/alib.h | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/amd/common/block') diff --git a/src/soc/amd/common/block/include/amdblocks/alib.h b/src/soc/amd/common/block/include/amdblocks/alib.h index 82d69358a3..3cae027c61 100644 --- a/src/soc/amd/common/block/include/amdblocks/alib.h +++ b/src/soc/amd/common/block/include/amdblocks/alib.h @@ -21,6 +21,7 @@ enum alib_dptc_parameter_ids { /* Picasso: SetVrmSocCurrentLimit (0xe) is not implemented in alib. */ ALIB_DPTC_VRM_SOC_CURRENT_LIMIT_ID = 0xe, + ALIB_DPTC_STT_ALPHA_APU = 0x20, ALIB_DPTC_STT_SKIN_TEMPERATURE_LIMIT_APU_ID = 0x22, ALIB_DPTC_STT_M1_ID = 0x26, ALIB_DPTC_STT_M2_ID = 0x27, -- cgit v1.2.3