From d828482c9b64d5bc7e99f756753fa197a740768b Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 28 Jul 2021 14:15:44 +0200 Subject: soc/amd/common/block/include/acpimmio_map: add GPIO bank 3 to table GPIO bank 3 isn't used in coreboot, but the existence is documented in both the Picasso PPR #55570 Rev 3.16 and Cezanne PPR #56569 Rev 3.01 and for those two SoCs all 4 banks are covered by the corresponding Memory32Fixed region in the DSDT. Signed-off-by: Felix Held Change-Id: Id444a97a398d7e3abfd1f5c4a32e762ee6ff68f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56674 Reviewed-by: Marshall Dawson Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/include/amdblocks/acpimmio_map.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/soc/amd/common/block') diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h index 176dc2b9a6..ebfc0395e9 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h @@ -72,6 +72,8 @@ * +---------------------------------------------------------------------------+ * |0x1700 GPIO configuration registers bank 2 (following bank 1) | * +---------------------------------------------------------------------------+ + * |0x1800 GPIO configuration registers bank 3 (following bank 2) | + * +---------------------------------------------------------------------------+ * |0x1c00 xHCI Power Management registers | * +---------------------------------------------------------------------------+ * |0x1d00 Wake device (AC DC timer) | -- cgit v1.2.3