From 3bad01373d771d9fce8ae7d667b2e3a3c2267d6d Mon Sep 17 00:00:00 2001 From: Kangheui Won Date: Fri, 23 Apr 2021 16:37:44 +1000 Subject: soc/amd/picasso: move PSP_SRAM addrs to separate header These addresses will be changed in cezanne. Before start working on cezanne, move these out to separate header as a clean-up. TEST=emerge-zork coreboot Signed-off-by: Kangheui Won Change-Id: I2499281d250aae701f86bfcc87c7681e5b684b6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52625 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- .../block/cpu/noncar/memlayout_psp_verstage.ld | 28 +--------------------- 1 file changed, 1 insertion(+), 27 deletions(-) (limited to 'src/soc/amd/common/block') diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_psp_verstage.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_psp_verstage.ld index aa27bae1d4..cc9ebc0827 100644 --- a/src/soc/amd/common/block/cpu/noncar/memlayout_psp_verstage.ld +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_psp_verstage.ld @@ -3,33 +3,7 @@ #include #include #include - -/* TODO: Move defines to SoC-specific header file to allow SoC specific values if needed. */ - -/* - * Start of available space is 0x15000 and this is where the - * header for the user app (verstage) must be mapped. - * Size is 0x28000 bytes - */ -#define PSP_SRAM_START 0x15000 -#define PSP_SRAM_SIZE 160K - -#define VERSTAGE_START 0x15000 - -/* - * The temp stack can be made much smaller if needed - even 256 bytes - * should be sufficient. This is just for the function mapping the - * actual stack. - */ -#define PSP_VERSTAGE_TEMP_STACK_START 0x32000 -#define PSP_VERSTAGE_TEMP_STACK_SIZE 4K - -/* - * The top of the stack must be 4k aligned, so set the bottom as 4k aligned - * and make the size a multiple of 4k - */ -#define PSP_VERSTAGE_STACK_START 0x33000 -#define PSP_VERSTAGE_STACK_SIZE 40K +#include ENTRY(_psp_vs_start) SECTIONS -- cgit v1.2.3