From f09b4b6beed16d964527d26700df6d350e3aeab0 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Mon, 6 Jul 2020 23:35:40 -0600 Subject: soc/amd/common: Refactor and consolidate code for spi base Previously, the spi base address code was using a number of different functions in a way that didn't work for use on the PSP. This patch consolidates all of that to a single saved value that gets the LPC SPI base address by default on X86, and allows the PSP to set it to a different value. BUG=b:159811539 TEST=Build with following patch to set the SPI speed in psp_verstage. Signed-off-by: Martin Roth Change-Id: I50d9de269bcb88fbf510056a6216e22a050cae6b Reviewed-on: https://review.coreboot.org/c/coreboot/+/43307 Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/spi/fch_spi.c | 29 +++++++++++++++-------------- src/soc/amd/common/block/spi/fch_spi_ctrl.c | 23 ++++++++++------------- 2 files changed, 25 insertions(+), 27 deletions(-) (limited to 'src/soc/amd/common/block/spi') diff --git a/src/soc/amd/common/block/spi/fch_spi.c b/src/soc/amd/common/block/spi/fch_spi.c index bf64c3f260..bac1452709 100644 --- a/src/soc/amd/common/block/spi/fch_spi.c +++ b/src/soc/amd/common/block/spi/fch_spi.c @@ -4,28 +4,30 @@ #include #include #include +#include #include #include #include -static uintptr_t fch_spi_base(void) -{ - uintptr_t base; - - base = lpc_get_spibase(); +static uintptr_t spi_base; - if (base) - return base; +void spi_set_base(void *base) +{ + spi_base = (uintptr_t)base; +} - lpc_set_spibase(SPI_BASE_ADDRESS); - lpc_enable_spi_rom(SPI_ROM_ENABLE); +uintptr_t spi_get_bar(void) +{ + if (ENV_X86 && !spi_base) + spi_set_base((void *)lpc_get_spibase()); + ASSERT(spi_base); - return SPI_BASE_ADDRESS; + return spi_base; } static void fch_spi_set_spi100(int norm, int fast, int alt, int tpm) { - uintptr_t base = fch_spi_base(); + uintptr_t base = spi_get_bar(); write16((void *)(base + SPI100_SPEED_CONFIG), SPI_SPEED_CFG(norm, fast, alt, tpm)); write16((void *)(base + SPI100_ENABLE), SPI_USE_SPI100); @@ -33,7 +35,7 @@ static void fch_spi_set_spi100(int norm, int fast, int alt, int tpm) static void fch_spi_disable_4dw_burst(void) { - uintptr_t base = fch_spi_base(); + uintptr_t base = spi_get_bar(); uint16_t val = read16((void *)(base + SPI100_HOST_PREF_CONFIG)); write16((void *)(base + SPI100_HOST_PREF_CONFIG), val & ~SPI_RD4DW_EN_HOST); @@ -41,7 +43,7 @@ static void fch_spi_disable_4dw_burst(void) static void fch_spi_set_read_mode(u32 mode) { - uintptr_t base = fch_spi_base(); + uintptr_t base = spi_get_bar(); uint32_t val = read32((void *)(base + SPI_CNTRL0)) & ~SPI_READ_MODE_MASK; write32((void *)(base + SPI_CNTRL0), val | SPI_READ_MODE(mode)); @@ -77,7 +79,6 @@ void fch_spi_config_modes(void) void fch_spi_early_init(void) { - lpc_set_spibase(SPI_BASE_ADDRESS); lpc_enable_spi_rom(SPI_ROM_ENABLE); lpc_enable_spi_prefetch(); fch_spi_disable_4dw_burst(); diff --git a/src/soc/amd/common/block/spi/fch_spi_ctrl.c b/src/soc/amd/common/block/spi/fch_spi_ctrl.c index 13ad0cd32d..0be6b0e72f 100644 --- a/src/soc/amd/common/block/spi/fch_spi_ctrl.c +++ b/src/soc/amd/common/block/spi/fch_spi_ctrl.c @@ -30,26 +30,24 @@ #define SPI_FIFO_RD_PTR_SHIFT 16 #define SPI_FIFO_RD_PTR_MASK 0x7f -static uint32_t spibar; - -static inline uint8_t spi_read8(uint8_t reg) +static uint8_t spi_read8(uint8_t reg) { - return read8((void *)(spibar + reg)); + return read8((void *)(spi_get_bar() + reg)); } -static inline uint32_t spi_read32(uint8_t reg) +static uint32_t spi_read32(uint8_t reg) { - return read32((void *)(spibar + reg)); + return read32((void *)(spi_get_bar() + reg)); } -static inline void spi_write8(uint8_t reg, uint8_t val) +static void spi_write8(uint8_t reg, uint8_t val) { - write8((void *)(spibar + reg), val); + write8((void *)(spi_get_bar() + reg), val); } -static inline void spi_write32(uint8_t reg, uint32_t val) +static void spi_write32(uint8_t reg, uint32_t val) { - write32((void *)(spibar + reg), val); + write32((void *)(spi_get_bar() + reg), val); } static void dump_state(const char *str, u8 phase) @@ -64,7 +62,7 @@ static void dump_state(const char *str, u8 phase) printk(BIOS_DEBUG, "Cntrl0: %x\n", spi_read32(SPI_CNTRL0)); printk(BIOS_DEBUG, "Status: %x\n", spi_read32(SPI_STATUS)); - addr = spibar + SPI_FIFO; + addr = spi_get_bar() + SPI_FIFO; if (phase == 0) { dump_size = spi_read8(SPI_TX_BYTE_COUNT); printk(BIOS_DEBUG, "TxByteCount: %x\n", dump_size); @@ -111,8 +109,7 @@ static int execute_command(void) void spi_init(void) { - spibar = lpc_get_spibase(); - printk(BIOS_DEBUG, "%s: Spibar at 0x%08x\n", __func__, spibar); + printk(BIOS_DEBUG, "%s: SPI BAR at 0x%08lx\n", __func__, spi_get_bar()); } static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, -- cgit v1.2.3