From 063fc1747aec2fb9f32756a800a89c5b9beeb0f8 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 9 Feb 2021 01:07:00 +0100 Subject: soc/amd: Move global_smi_enable to common/blocks/smi/smi_util MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I4410772a8d3f2dedbb96601d87efb23b14e5f438 Signed-off-by: Kyösti Mälkki Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/42989 Reviewed-by: Marshall Dawson Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/smi/smi_util.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src/soc/amd/common/block/smi') diff --git a/src/soc/amd/common/block/smi/smi_util.c b/src/soc/amd/common/block/smi/smi_util.c index dcf0c84b0a..1e4561d7a5 100644 --- a/src/soc/amd/common/block/smi/smi_util.c +++ b/src/soc/amd/common/block/smi/smi_util.c @@ -56,6 +56,15 @@ void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level) smi_write32(SMI_REG_SMITRIG0, reg32); } +/** Set the EOS bit and enable SMI generation from southbridge */ +void global_smi_enable(void) +{ + uint32_t reg = smi_read32(SMI_REG_SMITRIG0); + reg &= ~SMITRG0_SMIENB; /* Enable SMI generation */ + reg |= SMITRG0_EOS; /* Set EOS bit */ + smi_write32(SMI_REG_SMITRIG0, reg); +} + void soc_route_sci(uint8_t event) { smi_write8(SMI_SCI_MAP(event), event); -- cgit v1.2.3