From 3d2e18ad50d6dd0e93af1bb6efad20b4faede3b3 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Tue, 28 Jan 2020 11:20:05 -0700 Subject: soc/amd: unify SMBus support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SMBus support is identical between stoneyridge and picasso. Unify on common support code. Change-Id: Ic3412c5ee67977a45c50b68f36acc45c3d560db5 Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/c/coreboot/+/38616 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons Reviewed-by: Marshall Dawson --- src/soc/amd/common/block/smbus/Kconfig | 5 + src/soc/amd/common/block/smbus/Makefile.inc | 7 + src/soc/amd/common/block/smbus/sm.c | 102 +++++++++++++++ src/soc/amd/common/block/smbus/smbus.c | 196 ++++++++++++++++++++++++++++ 4 files changed, 310 insertions(+) create mode 100644 src/soc/amd/common/block/smbus/Kconfig create mode 100644 src/soc/amd/common/block/smbus/Makefile.inc create mode 100644 src/soc/amd/common/block/smbus/sm.c create mode 100644 src/soc/amd/common/block/smbus/smbus.c (limited to 'src/soc/amd/common/block/smbus') diff --git a/src/soc/amd/common/block/smbus/Kconfig b/src/soc/amd/common/block/smbus/Kconfig new file mode 100644 index 0000000000..dd54b638ea --- /dev/null +++ b/src/soc/amd/common/block/smbus/Kconfig @@ -0,0 +1,5 @@ +config SOC_AMD_COMMON_BLOCK_SMBUS + bool + default n + help + Select this option to add FCH SMBus controller functions to the build. diff --git a/src/soc/amd/common/block/smbus/Makefile.inc b/src/soc/amd/common/block/smbus/Makefile.inc new file mode 100644 index 0000000000..cfc954ec4f --- /dev/null +++ b/src/soc/amd/common/block/smbus/Makefile.inc @@ -0,0 +1,7 @@ +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SMBUS),y) + +romstage-y += smbus.c +ramstage-y += smbus.c +ramstage-y += sm.c + +endif diff --git a/src/soc/amd/common/block/smbus/sm.c b/src/soc/amd/common/block/smbus/sm.c new file mode 100644 index 0000000000..6ecf1cd998 --- /dev/null +++ b/src/soc/amd/common/block/smbus/sm.c @@ -0,0 +1,102 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* +* The southbridge enables all USB controllers by default in SMBUS Control. +* The southbridge enables SATA by default in SMBUS Control. +*/ + +static void sm_init(struct device *dev) +{ + setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS); +} + +static u32 get_sm_mmio(struct device *dev) +{ + struct resource *res; + struct bus *pbus; + + pbus = get_pbus_smbus(dev); + res = find_resource(pbus->dev, 0x90); + if (res->base == SMB_BASE_ADDR) + return ACPIMMIO_SMBUS_BASE; + + return ACPIMMIO_ASF_BASE; +} + +static int lsmbus_recv_byte(struct device *dev) +{ + u8 device; + + device = dev->path.i2c.device; + return do_smbus_recv_byte(get_sm_mmio(dev), device); +} + +static int lsmbus_send_byte(struct device *dev, u8 val) +{ + u8 device; + + device = dev->path.i2c.device; + return do_smbus_send_byte(get_sm_mmio(dev), device, val); +} + +static int lsmbus_read_byte(struct device *dev, u8 address) +{ + u8 device; + + device = dev->path.i2c.device; + return do_smbus_read_byte(get_sm_mmio(dev), device, address); +} + +static int lsmbus_write_byte(struct device *dev, u8 address, u8 val) +{ + u8 device; + + device = dev->path.i2c.device; + return do_smbus_write_byte(get_sm_mmio(dev), device, address, val); +} +static struct smbus_bus_operations lops_smbus_bus = { + .recv_byte = lsmbus_recv_byte, + .send_byte = lsmbus_send_byte, + .read_byte = lsmbus_read_byte, + .write_byte = lsmbus_write_byte, +}; + +static struct pci_operations lops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; +static struct device_operations smbus_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = pci_dev_enable_resources, + .init = sm_init, + .scan_bus = scan_smbus, + .ops_pci = &lops_pci, + .ops_smbus_bus = &lops_smbus_bus, +}; +static const struct pci_driver smbus_driver __pci_driver = { + .ops = &smbus_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_CZ_SMBUS, +}; diff --git a/src/soc/amd/common/block/smbus/smbus.c b/src/soc/amd/common/block/smbus/smbus.c new file mode 100644 index 0000000000..5474c5cd45 --- /dev/null +++ b/src/soc/amd/common/block/smbus/smbus.c @@ -0,0 +1,196 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +/* + * Between 1-10 seconds, We should never timeout normally + * Longer than this is just painful when a timeout condition occurs. + */ +#define SMBUS_TIMEOUT (100 * 1000 * 10) + +static u8 controller_read8(uintptr_t base, u8 reg) +{ + switch (base) { + case ACPIMMIO_SMBUS_BASE: + return smbus_read8(reg); + case ACPIMMIO_ASF_BASE: + return asf_read8(reg); + default: + printk(BIOS_ERR, "Error attempting to read SMBus at address 0x%lx\n", + base); + } + return 0xff; +} + +static void controller_write8(uintptr_t base, u8 reg, u8 val) +{ + switch (base) { + case ACPIMMIO_SMBUS_BASE: + smbus_write8(reg, val); + break; + case ACPIMMIO_ASF_BASE: + asf_write8(reg, val); + break; + default: + printk(BIOS_ERR, "Error attempting to write SMBus at address 0x%lx\n", + base); + } +} + +static int smbus_wait_until_ready(uintptr_t mmio) +{ + u32 loops; + loops = SMBUS_TIMEOUT; + do { + u8 val; + val = controller_read8(mmio, SMBHSTSTAT); + val &= SMBHST_STAT_VAL_BITS; + if (val == 0) { /* ready now */ + return 0; + } + controller_write8(mmio, SMBHSTSTAT, val); + } while (--loops); + return -2; /* time out */ +} + +static int smbus_wait_until_done(uintptr_t mmio) +{ + u32 loops; + loops = SMBUS_TIMEOUT; + do { + u8 val; + + val = controller_read8(mmio, SMBHSTSTAT); + val &= SMBHST_STAT_VAL_BITS; /* mask off reserved bits */ + if (val & SMBHST_STAT_ERROR_BITS) + return -5; /* error */ + if (val == SMBHST_STAT_NOERROR) { + controller_write8(mmio, SMBHSTSTAT, val); /* clr sts */ + return 0; + } + } while (--loops); + return -3; /* timeout */ +} + +int do_smbus_recv_byte(uintptr_t mmio, u8 device) +{ + u8 byte; + + if (smbus_wait_until_ready(mmio) < 0) + return -2; /* not ready */ + + /* set the device I'm talking to */ + controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 1); + + byte = controller_read8(mmio, SMBHSTCTRL); + byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */ + byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BTE_RW; /* set mode, start */ + controller_write8(mmio, SMBHSTCTRL, byte); + + /* poll for transaction completion */ + if (smbus_wait_until_done(mmio) < 0) + return -3; /* timeout or error */ + + /* read results of transaction */ + byte = controller_read8(mmio, SMBHSTDAT0); + + return byte; +} + +int do_smbus_send_byte(uintptr_t mmio, u8 device, u8 val) +{ + u8 byte; + + if (smbus_wait_until_ready(mmio) < 0) + return -2; /* not ready */ + + /* set the command... */ + controller_write8(mmio, SMBHSTDAT0, val); + + /* set the device I'm talking to */ + controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 0); + + byte = controller_read8(mmio, SMBHSTCTRL); + byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */ + byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BTE_RW; /* set mode, start */ + controller_write8(mmio, SMBHSTCTRL, byte); + + /* poll for transaction completion */ + if (smbus_wait_until_done(mmio) < 0) + return -3; /* timeout or error */ + + return 0; +} + +int do_smbus_read_byte(uintptr_t mmio, u8 device, u8 address) +{ + u8 byte; + + if (smbus_wait_until_ready(mmio) < 0) + return -2; /* not ready */ + + /* set the command/address... */ + controller_write8(mmio, SMBHSTCMD, address & 0xff); + + /* set the device I'm talking to */ + controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 1); + + byte = controller_read8(mmio, SMBHSTCTRL); + byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */ + byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BDT_RW; /* set mode, start */ + controller_write8(mmio, SMBHSTCTRL, byte); + + /* poll for transaction completion */ + if (smbus_wait_until_done(mmio) < 0) + return -3; /* timeout or error */ + + /* read results of transaction */ + byte = controller_read8(mmio, SMBHSTDAT0); + + return byte; +} + +int do_smbus_write_byte(uintptr_t mmio, u8 device, u8 address, u8 val) +{ + u8 byte; + + if (smbus_wait_until_ready(mmio) < 0) + return -2; /* not ready */ + + /* set the command/address... */ + controller_write8(mmio, SMBHSTCMD, address & 0xff); + + /* set the device I'm talking to */ + controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 0); + + /* output value */ + controller_write8(mmio, SMBHSTDAT0, val); + + byte = controller_read8(mmio, SMBHSTCTRL); + byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */ + byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BDT_RW; /* set mode, start */ + controller_write8(mmio, SMBHSTCTRL, byte); + + /* poll for transaction completion */ + if (smbus_wait_until_done(mmio) < 0) + return -3; /* timeout or error */ + + return 0; +} -- cgit v1.2.3