From bf1712422a1978759e41ed985fb5296e85255d70 Mon Sep 17 00:00:00 2001 From: Richard Spiegel Date: Wed, 21 Aug 2019 10:09:51 -0700 Subject: soc/amd/stoneyridge: Use new common SPI code Use the new SPI code from common folder, delete spi.c. SPI related macros must be single defined, in southbridge.h if they are used by files other than the common SPI code, fch_spi.h if they are only used by the common SPI code. The only exception is SPI_FIFO_DEPTH which must be in southbridge.h, because it can change between SOC. BUG=b:136595978 TEST=Build and boot grunt using new SPI code, with debug enabled. Check output. Change-Id: I639973d993316a10daa7564462e689b2c183f536 Signed-off-by: Richard Spiegel Reviewed-on: https://review.coreboot.org/c/coreboot/+/35019 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan --- src/soc/amd/common/block/include/amdblocks/fch_spi.h | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'src/soc/amd/common/block/include') diff --git a/src/soc/amd/common/block/include/amdblocks/fch_spi.h b/src/soc/amd/common/block/include/amdblocks/fch_spi.h index 24cfbfc74a..cfbdf198b5 100644 --- a/src/soc/amd/common/block/include/amdblocks/fch_spi.h +++ b/src/soc/amd/common/block/include/amdblocks/fch_spi.h @@ -28,13 +28,21 @@ #define IDCODE_LEN (IDCODE_CONT_LEN + IDCODE_PART_LEN) /* SPI MMIO registers */ -#define SPI_CNTRL0 0x00 -#define SPI_ACCESS_MAC_ROM_EN BIT(22) #define SPI_RESTRICTED_CMD1 0x04 #define SPI_RESTRICTED_CMD2 0x08 #define SPI_CNTRL1 0x0c #define SPI_CMD_CODE 0x45 #define SPI_CMD_TRIGGER 0x47 +#define SPI_CMD_TRIGGER_EXECUTE BIT(7) +#define SPI_TX_BYTE_COUNT 0x48 +#define SPI_RX_BYTE_COUNT 0x4b +#define SPI_STATUS 0x4c +#define SPI_DONE_BYTE_COUNT_SHIFT 0 +#define SPI_DONE_BYTE_COUNT_MASK 0xff +#define SPI_FIFO_WR_PTR_SHIFT 8 +#define SPI_FIFO_WR_PTR_MASK 0x7f +#define SPI_FIFO_RD_PTR_SHIFT 16 +#define SPI_FIFO_RD_PTR_MASK 0x7f /* Special SST write commands */ #define CMD_SST_BP 0x02 /* Byte Program */ -- cgit v1.2.3