From 7ae4a268eb244ac5ab80ed9db5887fe35b71a49e Mon Sep 17 00:00:00 2001 From: Richard Spiegel Date: Tue, 24 Sep 2019 17:56:34 -0700 Subject: soc/amd/common/block/spi/fch_spi_ctrl.c: Fix SPI vendor id code All solid state devices have vendor id defined by JEDEC specification JEP106, which originally allocated only 7 bits for it plus parity. When number of vendors exploded beyond 126, a banking proposition came maintaining compatibility with older vendors while allowing for 4 extra bits (16 banks) through the introduction of the concept "Continuation code", denoted by the byte value of 0x7f. Examples: 0xfe, 0x60, 0x18, 0x00, 0x00 => vendor 0xfe of bank o 0x7f, 0x7f, 0xfe, 0x60, 0x18 => vendor 0xfe of bank 2 BUG=b:141535133 TEST=Build and boot grunt. Change-Id: I16c5df70b8ba65017d1a45c79e90a76d1f78550c Signed-off-by: Richard Spiegel Reviewed-on: https://review.coreboot.org/c/coreboot/+/35589 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan --- src/soc/amd/common/block/include/amdblocks/fch_spi.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'src/soc/amd/common/block/include') diff --git a/src/soc/amd/common/block/include/amdblocks/fch_spi.h b/src/soc/amd/common/block/include/amdblocks/fch_spi.h index cfbdf198b5..8e288283b1 100644 --- a/src/soc/amd/common/block/include/amdblocks/fch_spi.h +++ b/src/soc/amd/common/block/include/amdblocks/fch_spi.h @@ -23,7 +23,14 @@ #define WORD_TO_DWORD_UPPER(x) ((x << 16) & 0xffff0000) #define SPI_PAGE_WRITE 0x02 #define SPI_WRITE_ENABLE 0x06 -#define IDCODE_CONT_LEN 0 +/* + * IDCODE_CONT_LEN may be redefined if a device needs to declare a + * larger "shift" value. IDCODE_PART_LEN generally shouldn't be + * changed. This is the max number of bytes probe functions may + * examine when looking up part-specific identification info. + */ +#define IDCODE_CONT_CODE 0x7f +#define IDCODE_CONT_LEN 1 /* currently support only bank 0 */ #define IDCODE_PART_LEN 5 #define IDCODE_LEN (IDCODE_CONT_LEN + IDCODE_PART_LEN) -- cgit v1.2.3