From 556d1cc17f34615e3a08ccc9a48820a304a789a8 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 2 Feb 2022 22:11:52 +0100 Subject: soc/amd/*/i2c: factor out common I2C pad configuration The I2C pad control registers of Picasso and Cezanne are identical and the one of Sabrina is a superset of it, so factor out the functionality. To avoid having devicetree settings that contain raw register bits, the i2c_pad_control struct is introduced and used. The old Picasso code for this had the RX level hard-coded for 3.3V I2C interfaces, so keep it this way in this patch but add a TODO for future improvements. Signed-off-by: Felix Held Change-Id: I1d70329644b68be3c4a1602f748e09db20cf6de1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61568 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/soc/amd/common/block/include/amdblocks/i2c.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'src/soc/amd/common/block/include') diff --git a/src/soc/amd/common/block/include/amdblocks/i2c.h b/src/soc/amd/common/block/include/amdblocks/i2c.h index 6660e3779c..54651a9321 100644 --- a/src/soc/amd/common/block/include/amdblocks/i2c.h +++ b/src/soc/amd/common/block/include/amdblocks/i2c.h @@ -56,6 +56,21 @@ struct soc_i2c_peripheral_reset_info { size_t num_pins; }; +enum i2c_pad_rx_level { + I2C_PAD_RX_NO_CHANGE, + I2C_PAD_RX_OFF, + I2C_PAD_RX_3_3V, + I2C_PAD_RX_1_8V, +}; + +struct i2c_pad_control { + enum i2c_pad_rx_level rx_level; +}; + +void fch_i2c_pad_init(unsigned int bus, + enum i2c_speed speed, + const struct i2c_pad_control *ctrl); + /* Helper function to perform misc I2C configuration specific to SoC. */ void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg); -- cgit v1.2.3