From 2446c1e9e99e6448f5f62c7a4f9c50dceec2b25e Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Thu, 9 Jul 2020 07:13:37 +0300 Subject: arch/x86: Drop CBMEM_TOP_BACKUP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Code has evolved such that there seems to be little use for global definition of cbmem_top_chipset(). Even for AMD we had three different implementations. Change-Id: I44805aa49eab526b940e57bd51cd1d9ae0377b4b Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/43326 Reviewed-by: Angel Pons Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/include/amdblocks/biosram.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/soc/amd/common/block/include') diff --git a/src/soc/amd/common/block/include/amdblocks/biosram.h b/src/soc/amd/common/block/include/amdblocks/biosram.h index 39ce112c0e..226fc173d4 100644 --- a/src/soc/amd/common/block/include/amdblocks/biosram.h +++ b/src/soc/amd/common/block/include/amdblocks/biosram.h @@ -5,6 +5,14 @@ #include +/* Any new chipset and board must implement cbmem_top() for both + * romstage and ramstage to support early features like COLLECT_TIMESTAMPS + * and CBMEM_CONSOLE. With AMD it is necessary to have cbmem_top() + * value stored in nvram to enable early recovery on S3 path. + */ +void backup_top_of_low_cacheable(uintptr_t ramtop); +uintptr_t restore_top_of_low_cacheable(void); + /* Returns the bootblock C entry point for APs */ void *get_ap_entry_ptr(void); /* Used by BSP to store the bootblock entry point for APs */ -- cgit v1.2.3