From 78cbcefb7662b5f749b5583dce2c78b100b9d58e Mon Sep 17 00:00:00 2001 From: Felix Held Date: Sat, 25 Mar 2023 04:58:40 +0100 Subject: soc/amd/common/acpi/cpu_power_state: introduce & use get_pstate_latency On the Zen-based CPUs, the transition and bus master latency are always written as 0, but on but on Stoneyridge hardware-dependent values are used. Introduce get_pstate_latency that returns 0 for all non-CAR AMD CPUs. Signed-off-by: Felix Held Change-Id: I81086fa64909c7350b3b171ea6ea9b46f1708f67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74024 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/amd/common/block/include/amdblocks/cpu.h | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/amd/common/block/include/amdblocks') diff --git a/src/soc/amd/common/block/include/amdblocks/cpu.h b/src/soc/amd/common/block/include/amdblocks/cpu.h index a6602336f5..4aa225bda3 100644 --- a/src/soc/amd/common/block/include/amdblocks/cpu.h +++ b/src/soc/amd/common/block/include/amdblocks/cpu.h @@ -18,6 +18,7 @@ union pstate_msr; /* proper definition is in soc/msr.h */ uint32_t get_uvolts_from_vid(uint16_t core_vid); uint32_t get_pstate_0_reg(void); +uint32_t get_pstate_latency(void); uint32_t get_pstate_core_freq(union pstate_msr pstate_reg); uint32_t get_pstate_core_uvolts(union pstate_msr pstate_reg); const acpi_cstate_t *get_cstate_config_data(size_t *size); -- cgit v1.2.3