From dba3229b90c7762e9f101cdcd036ca48c76f56bf Mon Sep 17 00:00:00 2001
From: Felix Held <felix.held@amd.corp-partner.google.com>
Date: Tue, 31 Mar 2020 23:54:44 +0200
Subject: soc/amd/common/psp: Move early init to soc

The initialization code in common//psp is very specific to Family 15h.
Move this to the stoneyridge directory.

BUG=b:130660285
TEST: Verify PSP functionality on google/grunt

Change-Id: Ice3d06d6437f59a529c26fc2359565c940d39482
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/2020365
Reviewed-by: Eric Peers <epeers@google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
---
 src/soc/amd/common/block/include/amdblocks/psp.h | 20 ++------------------
 1 file changed, 2 insertions(+), 18 deletions(-)

(limited to 'src/soc/amd/common/block/include/amdblocks/psp.h')

diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h
index 494f1744f0..42c802d51b 100644
--- a/src/soc/amd/common/block/include/amdblocks/psp.h
+++ b/src/soc/amd/common/block/include/amdblocks/psp.h
@@ -15,24 +15,8 @@
 #ifndef __AMD_PSP_H__
 #define __AMD_PSP_H__
 
-#include <amdblocks/agesawrapper.h>
-#include <soc/pci_devs.h>
-#include <types.h>
-
-/* Extra, Special Purpose Registers in the PSP PCI Config Space */
-
-/* PSP Mirror Features Capabilities and Control Register */
-#define PSP_PCI_MIRRORCTRL1_REG       0x44    /* PSP Mirror Ctrl Reg          */
-#define   PMNXTPTRW_MASK              0xff    /* PCI AFCR pointer mask        */
-#define   PMNXTPTRW_EXPOSE            0xa4    /* Pointer to expose the AFCR   */
-
-#define PSP_PCI_EXT_HDR_CTRL          0x48    /* Extra PCI Header Ctrl        */
-#define   MAGIC_ENABLES               0x34    /* Extra PCI HDR Ctl Enables    */
-
-#define PSP_MAILBOX_BASE              0x70    /* Mailbox offset from PCIe BAR */
-
-#define MSR_CU_CBBCFG                 0xc00110a2 /* PSP Pvt Blk Base Addr */
-#define   BAR3HIDE                    BIT(12) /* Bit to hide BAR3 addr */
+/* Get the mailbox base address - specific to family of device. */
+struct psp_mbox *soc_get_mbox_address(void);
 
 /* x86 to PSP commands */
 #define MBOX_BIOS_CMD_DRAM_INFO    0x01
-- 
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