From ba2533f0ee952a2bbe90ed60d5ab3d4c19513aa0 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Wed, 4 Sep 2019 11:00:06 -0600 Subject: soc/amd/common/lpc: Add decode disable function It is already trivial to set D14F3x44 to 0, but add a function to wipe both that and the settings in D14F3x48, along with x48's associated addresses. Change-Id: Ibec25562b2a1568681aea7caf86f00094c436a50 Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/35270 Tested-by: build bot (Jenkins) Reviewed-by: Richard Spiegel --- src/soc/amd/common/block/include/amdblocks/lpc.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/soc/amd/common/block/include/amdblocks/lpc.h') diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index 6b6745d9cb..f956ba3aa9 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -68,6 +68,7 @@ #define DECODE_IO_PORT_ENABLE2 BIT(18) #define DECODE_IO_PORT_ENABLE1 BIT(17) #define DECODE_IO_PORT_ENABLE0 BIT(16) +#define LPC_SYNC_TIMEOUT_COUNT_MASK (0xff << 8) #define LPC_SYNC_TIMEOUT_COUNT_ENABLE BIT(7) #define LPC_DECODE_RTC_IO_ENABLE BIT(6) #define DECODE_MEM_PORT_ENABLE0 BIT(5) @@ -134,6 +135,9 @@ #define PREFETCH_EN_SPI_FROM_HOST BIT(0) #define T_START_ENH BIT(3) +/* Clear all decoding to the LPC bus and erase any range registers associated + * with the enable bits. */ +void lpc_disable_decodes(void); /* LPC is typically enabled very early, but this function is last opportunity */ void soc_late_lpc_bridge_enable(void); void lpc_enable_port80(void); -- cgit v1.2.3