From 55fea11f2ff5d2c8880dfe66c07bfb39c63affb0 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Fri, 23 Jul 2021 16:43:18 -0600 Subject: soc/amd/common/block/cpu: Add support for cbfs_cache region This change adds the cbfs_cache region into the x86 memlayout. The SoC or mainboard can decide how big the region should be by specifying CBFS_CACHE_SIZE. BUG=b:179699789 TEST=Build guybrush and verify cbfs_cache region wasn't added. Signed-off-by: Raul E Rangel Change-Id: I268b6bc10906932ee94f795684a28cfac247a68c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56578 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian --- src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src/soc/amd/common/block/cpu/noncar') diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld index 005bde093b..a542b7d6ad 100644 --- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld @@ -25,6 +25,10 @@ BOOTBLOCK_ADDR = BOOTBLOCK_END - CONFIG_C_ENV_BOOTBLOCK_SIZE; * | | * reserved_dram_end +--------------------------------+ * | | + * | cbfs_cache (if reqd) | + * | (CBFS_CACHE_SIZE) | + * +--------------------------------+ VERSTAGE_ADDR + VERSTAGE_SIZE + * | | * | verstage (if reqd) | * | (VERSTAGE_SIZE) | * +--------------------------------+ VERSTAGE_ADDR @@ -95,6 +99,11 @@ SECTIONS VERSTAGE(CONFIG_VERSTAGE_ADDR, CONFIG_VERSTAGE_SIZE) #endif +#if CONFIG_CBFS_CACHE_SIZE > 0 + . = ALIGN(ARCH_CACHELINE_ALIGN_SIZE); + CBFS_CACHE(., CONFIG_CBFS_CACHE_SIZE) +#endif + EARLY_RESERVED_DRAM_END(.) #if CONFIG(PAYLOAD_PRELOAD) -- cgit v1.2.3