From 9065f4f8ed2facb60df3f4906b8e1e66e8958379 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Sat, 21 Nov 2020 02:12:54 +0100 Subject: soc/amd: move non-CAR linker scripts to common directory AMD family 17h and newer don't use cache as RAM, since the RAM is already initialized by the PSP when the x86 cores are released from reset. Therefore they use a different linker script as the rest of the x86 chips in coreboot do. Since there will be support for newer generations than Picasso will be added, move those linker scripts from soc/amd/picasso to soc/amd/common/block/cpu/noncar. TEST=Timeless build of amd/mandolin and amd/gardenia result in identical binaries. Change-Id: Ie60372aa498b6e505708f97213b502c9d0b3534b Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/47828 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- .../amd/common/block/cpu/noncar/memlayout_x86.ld | 116 +++++++++++++++++++++ 1 file changed, 116 insertions(+) create mode 100644 src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld (limited to 'src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld') diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld new file mode 100644 index 0000000000..369d43151e --- /dev/null +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +#define EARLY_RESERVED_DRAM_START(addr) SYMBOL(early_reserved_dram, addr) +#define EARLY_RESERVED_DRAM_END(addr) SYMBOL(eearly_reserved_dram, addr) + +#define PSP_SHAREDMEM_DRAM_START(addr) SYMBOL(psp_sharedmem_dram, addr) +#define PSP_SHAREDMEM_DRAM_END(addr) SYMBOL(epsp_sharedmem_dram, addr) + +/* + * + * +--------------------------------+ + * | | + * | | + * | | + * | | + * | | + * | | + * | | + * reserved_dram_end +--------------------------------+ + * | | + * | verstage (if reqd) | + * | (VERSTAGE_SIZE) | + * +--------------------------------+ VERSTAGE_ADDR + * | | + * | FSP-M | + * | (FSP_M_SIZE) | + * +--------------------------------+ FSP_M_ADDR + * | |X86_RESET_VECTOR = ROMSTAGE_ADDR + ROMSTAGE_SIZE - 0x10 + * | romstage | + * | (ROMSTAGE_SIZE) | + * +--------------------------------+ ROMSTAGE_ADDR + * | bootblock | + * | (C_ENV_BOOTBLOCK_SIZE) | + * +--------------------------------+ BOOTBLOCK_ADDR + * | Unused hole | + * +--------------------------------+ + * | FMAP cache (FMAP_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 + * | Early Timestamp region (512B) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + * | Preram CBMEM console | + * | (PRERAM_CBMEM_CONSOLE_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE + * | PSP shared (vboot workbuf) | + * |(VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + * | Transfer Info Structure | + * +--------------------------------+ PSP_SHAREDMEM_BASE + * | APOB (64KiB) | + * +--------------------------------+ PSP_APOB_DRAM_ADDRESS + * | Early BSP stack | + * | (EARLYRAM_BSP_STACK_SIZE) | + * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE + * | DRAM | + * +--------------------------------+ 0x100000 + * | Option ROM | + * +--------------------------------+ 0xc0000 + * | Legacy VGA | + * +--------------------------------+ 0xa0000 + * | DRAM | + * +--------------------------------+ 0x0 + */ +SECTIONS +{ + DRAM_START(0x0) + + EARLY_RESERVED_DRAM_START(CONFIG_EARLY_RESERVED_DRAM_BASE) + + EARLYRAM_STACK(., CONFIG_EARLYRAM_BSP_STACK_SIZE) + REGION(apob, CONFIG_PSP_APOB_DRAM_ADDRESS, 64K, 1) + +#if CONFIG(VBOOT) + PSP_SHAREDMEM_DRAM_START(CONFIG_PSP_SHAREDMEM_BASE) +#endif + +#include "memlayout_transfer_buffer.inc" + +#if CONFIG(VBOOT) + PSP_SHAREDMEM_DRAM_END(CONFIG_PSP_SHAREDMEM_BASE + CONFIG_PSP_SHAREDMEM_SIZE) +#endif + _ = ASSERT((CONFIG_BOOTBLOCK_ADDR + CONFIG_C_ENV_BOOTBLOCK_SIZE - 0x10) == CONFIG_X86_RESET_VECTOR, "Reset vector should be -0x10 from end of bootblock"); + _ = ASSERT(CONFIG_BOOTBLOCK_ADDR == ((CONFIG_BOOTBLOCK_ADDR + 0xFFFF) & 0xFFFF0000), "Bootblock must be 16 bit aligned"); + BOOTBLOCK(CONFIG_BOOTBLOCK_ADDR, CONFIG_C_ENV_BOOTBLOCK_SIZE) + ROMSTAGE(CONFIG_ROMSTAGE_ADDR, CONFIG_ROMSTAGE_SIZE) + REGION(fspm, CONFIG_FSP_M_ADDR, CONFIG_FSP_M_SIZE, 1) +#if CONFIG(VBOOT_SEPARATE_VERSTAGE) + VERSTAGE(CONFIG_VERSTAGE_ADDR, CONFIG_VERSTAGE_SIZE) +#endif + + EARLY_RESERVED_DRAM_END(.) + + RAMSTAGE(CONFIG_RAMBASE, 8M) +} + +#if ENV_BOOTBLOCK + +gdtptr16_offset = gdtptr16 & 0xffff; +nullidt_offset = nullidt & 0xffff; + +SECTIONS { + /* Trigger an error if I have an unusable start address */ + _TOO_LOW = CONFIG_X86_RESET_VECTOR - 0xfff0; + _bogus = ASSERT(_start16bit >= _TOO_LOW, "_start16bit too low. Please report."); + + . = CONFIG_X86_RESET_VECTOR; + .reset . : { + *(.reset); + . = 15; + BYTE(0x00); + } +} +#endif /* ENV_BOOTBLOCK */ -- cgit v1.2.3