From 7cee5661610fd52f32d51adc12ba86c28fed4739 Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Mon, 28 Dec 2020 14:52:11 +0800 Subject: soc/amd/picasso: Add STXS and CTXS method Add STXS and CTXS into gpiolib. We can align with Intel ACPI method for the better usage. This benefits acpi.c to be more clear, too. BUG=b:176270381 BRANCH=zork TEST=Confirm the Goodix touchscreen functional. Signed-off-by: Eric Lai Change-Id: If4fcd68496a712fdccf44b91a6192ef58a0a9733 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48943 Reviewed-by: Furquan Shaikh Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/soc/amd/common/acpi/gpio_bank_lib.asl | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'src/soc/amd/common/acpi') diff --git a/src/soc/amd/common/acpi/gpio_bank_lib.asl b/src/soc/amd/common/acpi/gpio_bank_lib.asl index 9686ddc1c9..f209f448c1 100644 --- a/src/soc/amd/common/acpi/gpio_bank_lib.asl +++ b/src/soc/amd/common/acpi/gpio_bank_lib.asl @@ -2,6 +2,9 @@ #include +#define GPIO_OUTPUT_SHIFT 22 +#define GPIO_OUTPUT_VALUE (1 << GPIO_OUTPUT_SHIFT) + /* Get pin control MMIO address */ Method (GPAD, 0x1) { @@ -117,3 +120,31 @@ Method (GPW3, 0x2) /* Arg1 - Value for control register */ GPSB (Arg0, 3, Arg1) } + +/* + * Set GPIO Output Value + * Arg0 - GPIO Number + */ +Method (STXS, 1, Serialized) +{ + OperationRegion (GPDW, SystemMemory, GPAD (Arg0), 4) + Field (GPDW, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + VAL0 |= GPIO_OUTPUT_VALUE +} + +/* + * Clear GPIO Output Value + * Arg0 - GPIO Number + */ +Method (CTXS, 1, Serialized) +{ + OperationRegion (GPDW, SystemMemory, GPAD (Arg0), 4) + Field (GPDW, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + VAL0 &= ~GPIO_OUTPUT_VALUE +} -- cgit v1.2.3