From 251d305e73f76ca3b63654273f3b2bb3de775457 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Thu, 2 May 2019 17:27:57 -0600 Subject: soc/amd/stoneyridge: Move GPIO support to common The banked GPIO functionality in the AcpiMmio block has been consistent since the Mullins product. Move the basic support into a common directory. Each product's pin availability, MUXes, and other details must remain specific to the product. The relocated source also drops the weak configure_gevent_smi() that reports SMI is not available. The stoneyridge port relies on SMI to do its initialization, similar to modern soc/intel devices. This is the plan for future soc/amd ports, so make a missing function a build error instead of a runtime warning. BUG=b:131682806 Change-Id: I9cda00210a74de2bd1308ad43e2b867d24a67845 Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/32651 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/amd/common/acpi/gpio_bank_lib.asl | 132 ++++++++++++++++++++++++++++++ 1 file changed, 132 insertions(+) create mode 100644 src/soc/amd/common/acpi/gpio_bank_lib.asl (limited to 'src/soc/amd/common/acpi') diff --git a/src/soc/amd/common/acpi/gpio_bank_lib.asl b/src/soc/amd/common/acpi/gpio_bank_lib.asl new file mode 100644 index 0000000000..8185c35ac5 --- /dev/null +++ b/src/soc/amd/common/acpi/gpio_bank_lib.asl @@ -0,0 +1,132 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +/* Get pin control MMIO address */ +Method (GPAD, 0x1) +{ + /* Arg0 - GPIO pin number */ + Return (Add(Multiply(Arg0, 4), ACPIMMIO_GPIO0_BASE)) +} + +/* Read pin control dword */ +Method (GPRD, 0x1, Serialized) +{ + /* Arg0 - GPIO pin control MMIO address */ + Store (Arg0, Local0) + OperationRegion (GPDW, SystemMemory, Local0, 4) + Field (GPDW, AnyAcc, NoLock, Preserve) { + TEMP, 32 + } + Return (TEMP) +} + +/* Write pin control dword */ +Method (GPWR, 0x2, Serialized) +{ + /* Arg0 - GPIO pin control MMIO address */ + /* Arg1 - Value for control register */ + Store (Arg0, Local0) + OperationRegion (GPDW, SystemMemory, Local0, 4) + Field (GPDW, AnyAcc, NoLock, Preserve) { + TEMP,32 + } + Store (Arg1, TEMP) +} + +Method (GPGB, 0x2) +{ + /* + * Returns the desired byte + * Arg0 - GPIO pin control MMIO address + * Arg1 - Desired byte (0 through 3) + */ + Store (Multiply(Arg1, 8), Local2) + Return (And(ShiftRight(GPRD(Arg0), Local2), 0x000000FF)) +} + +Method (GPSB, 0x3) +{ + /* + * Reads dword, replace byte, write back dword + * Arg0 - GPIO pin control MMIO address + * Arg1 - Desired byte (0 through 3) + * Arg2 - Value + */ + Store (Multiply(Arg1, 8), Local2) + And(ShiftRight(GPRD(Arg0), Local2), 0xFFFFFF00, Local3) + ShiftLeft (Or(And(Arg2, 0x000000FF),Local3), Local2, Local4) + GPWR (Arg0, Local4) +} + +/* Read pin control byte 0 */ +Method (GPR0, 0x1) +{ + /* Arg0 - GPIO pin control MMIO address */ + Return (GPGB(Arg0, 0)) +} + +/* Read pin control byte 1 */ +Method (GPR1, 0x1) +{ + /* Arg0 - GPIO pin control MMIO address */ + Return (GPGB(Arg0, 1)) +} + +/* Read pin control byte 2 */ +Method (GPR2, 0x1) +{ + /* Arg0 - GPIO pin control MMIO address */ + Return (GPGB(Arg0, 2)) +} + +/* Read pin control byte 3 */ +Method (GPR3, 0x1) +{ + Return (GPGB(Arg0, 3)) +} + +/* Write pin control byte 0 */ +Method (GPW0, 0x2) +{ + /* Arg0 - GPIO pin control MMIO address */ + /* Arg1 - Value for control register */ + GPSB (Arg0, 0, Arg1) +} + +/* Write pin control byte 1 */ +Method (GPW1, 0x2) +{ + /* Arg0 - GPIO pin control MMIO address */ + /* Arg1 - Value for control register */ + GPSB (Arg0, 1, Arg1) +} + +/* Write pin control byte 2 */ +Method (GPW2, 0x2) +{ + /* Arg0 - GPIO pin control MMIO address */ + /* Arg1 - Value for control register */ + GPSB (Arg0, 2, Arg1) +} + +/* Write pin control byte 3 */ +Method (GPW3, 0x2) +{ + /* Arg0 - GPIO pin control MMIO address */ + /* Arg1 - Value for control register */ + GPSB (Arg0, 3, Arg1) +} -- cgit v1.2.3