From ea0f225249221edc75640756889f9e67992c4b90 Mon Sep 17 00:00:00 2001
From: Matt Papageorge <matthewpapa07@gmail.com>
Date: Tue, 30 Mar 2021 11:41:22 -0500
Subject: soc/amd/cezanne: Pass DXIO and DDI Descriptors to FSP

This patch adds the functionality to write the DXIO and DDI descriptors
to the UPD data structure to the SoC code and adds the
mainboard_get_dxio_ddi_descriptors function to each mainboard using the
Cezanne SoC that gets called to get the descriptors from the board code.

Change-Id: I1cb36addcf0202cd56ce99e610a13d6d230bc981
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
---
 src/soc/amd/cezanne/fsp_m_params.c                 | 45 ++++++++++++++++++++++
 .../amd/cezanne/include/soc/platform_descriptors.h | 15 ++++++++
 2 files changed, 60 insertions(+)
 create mode 100644 src/soc/amd/cezanne/include/soc/platform_descriptors.h

(limited to 'src/soc/amd/cezanne')

diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c
index 083a82d90c..f24b601c70 100644
--- a/src/soc/amd/cezanne/fsp_m_params.c
+++ b/src/soc/amd/cezanne/fsp_m_params.c
@@ -2,8 +2,51 @@
 
 #include <amdblocks/apob_cache.h>
 #include <amdblocks/memmap.h>
+#include <assert.h>
 #include <console/uart.h>
 #include <fsp/api.h>
+#include <soc/platform_descriptors.h>
+#include <string.h>
+#include <types.h>
+
+static void fill_dxio_descriptors(FSP_M_CONFIG *mcfg,
+			const fsp_dxio_descriptor *descs, size_t num)
+{
+	size_t i;
+
+	ASSERT_MSG(num <= FSPM_UPD_DXIO_DESCRIPTOR_COUNT,
+			"Too many DXIO descriptors provided.");
+
+	for (i = 0; i < num; i++) {
+		memcpy(mcfg->dxio_descriptor[i], &descs[i], sizeof(mcfg->dxio_descriptor[0]));
+	}
+}
+
+static void fill_ddi_descriptors(FSP_M_CONFIG *mcfg,
+			const fsp_ddi_descriptor *descs, size_t num)
+{
+	size_t i;
+
+	ASSERT_MSG(num <= FSPM_UPD_DDI_DESCRIPTOR_COUNT,
+			"Too many DDI descriptors provided.");
+
+	for (i = 0; i < num; i++) {
+		memcpy(&mcfg->ddi_descriptor[i], &descs[i], sizeof(mcfg->ddi_descriptor[0]));
+	}
+}
+
+static void fsp_fill_pcie_ddi_descriptors(FSP_M_CONFIG *mcfg)
+{
+	const fsp_dxio_descriptor *fsp_dxio;
+	const fsp_ddi_descriptor *fsp_ddi;
+	size_t num_dxio;
+	size_t num_ddi;
+
+	mainboard_get_dxio_ddi_descriptors(&fsp_dxio, &num_dxio,
+						&fsp_ddi, &num_ddi);
+	fill_dxio_descriptors(mcfg, fsp_dxio, num_dxio);
+	fill_ddi_descriptors(mcfg, fsp_ddi, num_ddi);
+}
 
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 {
@@ -18,4 +61,6 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 	mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM);
 	mcfg->serial_port_baudrate = get_uart_baudrate();
 	mcfg->serial_port_refclk = uart_platform_refclk();
+
+	fsp_fill_pcie_ddi_descriptors(mcfg);
 }
diff --git a/src/soc/amd/cezanne/include/soc/platform_descriptors.h b/src/soc/amd/cezanne/include/soc/platform_descriptors.h
new file mode 100644
index 0000000000..d68cd7fab9
--- /dev/null
+++ b/src/soc/amd/cezanne/include/soc/platform_descriptors.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_PICASSO_PLATFORM_DESCRIPTORS_H
+#define AMD_PICASSO_PLATFORM_DESCRIPTORS_H
+
+#include <types.h>
+#include <platform_descriptors.h>
+#include <FspmUpd.h>
+
+/* Mainboard callback to obtain DXI/PCIe and DDI descriptors. */
+void mainboard_get_dxio_ddi_descriptors(
+		const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num,
+		const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num);
+
+#endif /* AMD_PICASSO_PLATFORM_DESCRIPTORS_H */
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