From cc975c5c65c27f13c00dc7eabec02386002a2c53 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Sat, 23 Jan 2021 00:18:08 +0100
Subject: soc/amd/cezanne/Kconfig: select missing SSE2 option

This will set the corresponding enable bit in CR4 in bootblock_crt0.S

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I648a83fbcb71456bf1e5b11c491e7cadc8e0e281
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
---
 src/soc/amd/cezanne/Kconfig | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/soc/amd/cezanne')

diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 08d8397bf6..9b766736f0 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -28,6 +28,7 @@ config SOC_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_BLOCK_SMI
 	select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
 	select SOC_AMD_COMMON_BLOCK_UART
+	select SSE2
 	select UDK_2017_BINDING
 	select X86_AMD_FIXED_MTRRS
 
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