From 9244358536aaecff29453b1693fdf202091878ef Mon Sep 17 00:00:00 2001 From: Tim Van Patten Date: Tue, 23 Aug 2022 16:06:33 -0600 Subject: soc/amd: Refactor DPTC Tablet Mode Refactor AMD DPTC tablet mode in preparation for adding low/no battery DPTC settings. 1. Refactor and simplify acpigen_write_alib_dptc() into the following functions: - acpigen_write_alib_dptc_default() - acpigen_write_alib_dptc_tablet() 2. Add device tree register value dptc_tablet_mode_enable to control whether DPTC tablet mode is enabled for a variant. 3. Add dptc.asl to perform the necessary ACPI checking before modifying the DPTC settings. BRANCH=none BUG=b:217911928 TEST=Build zork TEST=Build nipperkin TEST=Boot skyrim Change-Id: I2518fdd526868c9d5668a6018fd3570392e809c0 Signed-off-by: Tim Van Patten Reviewed-on: https://review.coreboot.org/c/coreboot/+/66994 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian --- src/soc/amd/cezanne/acpi/soc.asl | 4 +++- src/soc/amd/cezanne/chip.h | 6 +++--- src/soc/amd/cezanne/root_complex.c | 17 ++++++++++------- 3 files changed, 16 insertions(+), 11 deletions(-) (limited to 'src/soc/amd/cezanne') diff --git a/src/soc/amd/cezanne/acpi/soc.asl b/src/soc/amd/cezanne/acpi/soc.asl index bf2838a337..7e3a3ee6a8 100644 --- a/src/soc/amd/cezanne/acpi/soc.asl +++ b/src/soc/amd/cezanne/acpi/soc.asl @@ -27,10 +27,12 @@ Scope(\_SB) { #include +#include + #include "rtc_workaround.asl" /* - * Platform Wake Notify + * Platform Notify * * This is called by soc/amd/common/acpi/platform.asl. */ diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h index ab798be695..74f60ffaad 100644 --- a/src/soc/amd/cezanne/chip.h +++ b/src/soc/amd/cezanne/chip.h @@ -86,10 +86,10 @@ struct soc_amd_cezanne_config { uint32_t telemetry_vddcrsocfull_scale_current_mA; uint32_t telemetry_vddcrsocoffset; - /* Enable dptc for tablet mode */ - bool dptc_enable; + /* Enable dptc tablet mode */ + bool dptc_tablet_mode_enable; - /* STAPM Configuration for tablet mode (need enable dptc_enable first) */ + /* STAPM Configuration for tablet mode */ uint32_t fast_ppt_limit_tablet_mode_mW; uint32_t slow_ppt_limit_tablet_mode_mW; uint32_t sustained_power_limit_tablet_mode_mW; diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c index 075f1a1f76..c67a6f7481 100644 --- a/src/soc/amd/cezanne/root_complex.c +++ b/src/soc/amd/cezanne/root_complex.c @@ -186,21 +186,24 @@ static void acipgen_dptci(void) { const struct soc_amd_cezanne_config *config = config_of_soc(); - if (!config->dptc_enable) + if (!config->dptc_tablet_mode_enable) return; + /* DPTC is enabled. Always fill out the default DPTC values. */ struct dptc_input default_input = DPTC_INPUTS(config->thermctl_limit_degreeC, - config->sustained_power_limit_mW, - config->fast_ppt_limit_mW, - config->slow_ppt_limit_mW); + config->sustained_power_limit_mW, + config->fast_ppt_limit_mW, + config->slow_ppt_limit_mW); + acpigen_write_alib_dptc_default((uint8_t *)&default_input, sizeof(default_input)); + + /* Tablet Mode */ struct dptc_input tablet_mode_input = DPTC_INPUTS( config->thermctl_limit_tablet_mode_degreeC, config->sustained_power_limit_tablet_mode_mW, config->fast_ppt_limit_tablet_mode_mW, config->slow_ppt_limit_tablet_mode_mW); - - acpigen_write_alib_dptc((uint8_t *)&default_input, sizeof(default_input), - (uint8_t *)&tablet_mode_input, sizeof(tablet_mode_input)); + acpigen_write_alib_dptc_tablet((uint8_t *)&tablet_mode_input, + sizeof(tablet_mode_input)); } static void root_complex_fill_ssdt(const struct device *device) -- cgit v1.2.3