From 8180427a16ce0ae3138a6d3204ddd15ebd8142b3 Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Sun, 20 Nov 2022 20:30:18 -0700
Subject: soc/amd: Define post codes

For the most part, this doesn't change any post codes, simply making the
existing post-codes into macros.

picasso/romstage.c did get a couple of post codes removed to match the
other files.

The POST_ROMSTAGE and POST_BOOTBLOCK codes are intended to become global
at some point, while the POST_AGESA and POST_PSP codes would stay AMD
specific.

Change-Id: I007a09b6a3ed3280bac674cd74e298ec5c408ab7
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/soc/amd/cezanne/romstage.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'src/soc/amd/cezanne')

diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c
index b843bff7dc..2bf5e230c9 100644
--- a/src/soc/amd/cezanne/romstage.c
+++ b/src/soc/amd/cezanne/romstage.c
@@ -4,6 +4,7 @@
 #include <amdblocks/acpimmio.h>
 #include <amdblocks/memmap.h>
 #include <amdblocks/pmlib.h>
+#include <amdblocks/post_codes.h>
 #include <console/console.h>
 #include <cpu/cpu.h>
 #include <fsp/api.h>
@@ -12,7 +13,7 @@
 
 void __noreturn romstage_main(void)
 {
-	post_code(0x40);
+	post_code(POST_ROMSTAGE_MAIN);
 
 	/* Snapshot chipset state prior to any FSP call */
 	fill_chipset_state();
-- 
cgit v1.2.3