From 3f2844fb1ee51b879dee9824d53924ca7c3f5cff Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 23 Mar 2023 23:05:50 +0100 Subject: soc/amd/*/include/msr: add version number to SERIAL_VID_* define names Picasso and Cezanne use the serial voltage ID 2 standard to communicate the CPU voltage to the voltage regulator module on the mainboard, while Mendocino, Phoenix and Glinda use the serial voltage ID 3 standard for this. Both standards encode the voltage in a different way, so add the serial VID version number to the defines to clarify for which version the define is. Signed-off-by: Felix Held Change-Id: I8ddab8df27c86dc2c70a6dfb47908d9405d86240 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73994 Reviewed-by: Fred Reitberger Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier --- src/soc/amd/cezanne/acpi.c | 4 ++-- src/soc/amd/cezanne/include/soc/msr.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'src/soc/amd/cezanne') diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index f65973d979..43ed7fed05 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -150,8 +150,8 @@ uint32_t get_pstate_core_power(union pstate_msr pstate_reg) /* Voltage off for VID codes 0xF8 to 0xFF */ voltage_in_uvolts = 0; } else { - voltage_in_uvolts = - SERIAL_VID_MAX_MICROVOLTS - (SERIAL_VID_DECODE_MICROVOLTS * core_vid); + voltage_in_uvolts = SERIAL_VID_2_MAX_MICROVOLTS - + (SERIAL_VID_2_DECODE_MICROVOLTS * core_vid); } /* Power in mW */ diff --git a/src/soc/amd/cezanne/include/soc/msr.h b/src/soc/amd/cezanne/include/soc/msr.h index 2ce03ade8a..fdbe47e342 100644 --- a/src/soc/amd/cezanne/include/soc/msr.h +++ b/src/soc/amd/cezanne/include/soc/msr.h @@ -23,8 +23,8 @@ union pstate_msr { #define PSTATE_DEF_CORE_FREQ_BASE 25 /* Value defined in Serial VID Interface 2.0 spec (#48022, NDA only) */ -#define SERIAL_VID_DECODE_MICROVOLTS 6250 -#define SERIAL_VID_MAX_MICROVOLTS 1550000L +#define SERIAL_VID_2_DECODE_MICROVOLTS 6250 +#define SERIAL_VID_2_MAX_MICROVOLTS 1550000L #define MSR_CPPC_CAPABILITY_1 0xc00102b0 #define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24 -- cgit v1.2.3