From b9e8044b28155747024bc5d74d9ea55ed94a60e3 Mon Sep 17 00:00:00 2001
From: Raul E Rangel <rrangel@chromium.org>
Date: Fri, 5 Feb 2021 15:53:04 -0700
Subject: soc/amd/cezanne/romstage: Store early dram region

Needed so we can reserve the memory.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8f5bb9d97932f75ca4ce22fbe9df4c0148acbea5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/soc/amd/cezanne/romstage.c | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src/soc/amd/cezanne/romstage.c')

diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c
index c7e7e5cba4..773c6a97d5 100644
--- a/src/soc/amd/cezanne/romstage.c
+++ b/src/soc/amd/cezanne/romstage.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <acpi/acpi.h>
+#include <amdblocks/memmap.h>
 #include <arch/cpu.h>
 #include <console/console.h>
 #include <console/uart.h>
@@ -33,5 +34,7 @@ asmlinkage void car_stage_entry(void)
 
 	fsp_memory_init(acpi_is_wakeup_s3());
 
+	memmap_stash_early_dram_usage();
+
 	run_ramstage();
 }
-- 
cgit v1.2.3