From 44f41537af4022ce8d8c4fadb6b690b3ec6f8c61 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Wed, 9 Dec 2020 02:01:16 +0100
Subject: soc/amd/cezanne: add 0xcf9 reset

Change-Id: Ibb78661c102e0d0327f3e74173bf98bc40e13960
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48488
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/cezanne/reset.c | 43 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)
 create mode 100644 src/soc/amd/cezanne/reset.c

(limited to 'src/soc/amd/cezanne/reset.c')

diff --git a/src/soc/amd/cezanne/reset.c b/src/soc/amd/cezanne/reset.c
new file mode 100644
index 0000000000..89b5b809d6
--- /dev/null
+++ b/src/soc/amd/cezanne/reset.c
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/io.h>
+#include <cf9_reset.h>
+#include <reset.h>
+#include <soc/reset.h>
+#include <soc/southbridge.h>
+#include <amdblocks/acpimmio.h>
+#include <amdblocks/reset.h>
+
+void set_warm_reset_flag(void)
+{
+	uint8_t ncp = inw(NCP_ERR);
+
+	outb(NCP_ERR, ncp | NCP_WARM_BOOT);
+}
+
+int is_warm_reset(void)
+{
+	return !!(inb(NCP_ERR) & NCP_WARM_BOOT);
+}
+
+void do_cold_reset(void)
+{
+	/* De-assert and then assert all PwrGood signals on CF9 reset. */
+	pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) |
+		TOGGLE_ALL_PWR_GOOD);
+	outb(RST_CPU | SYS_RST, RST_CNT);
+}
+
+void do_warm_reset(void)
+{
+	set_warm_reset_flag();
+
+	/* Assert reset signals only. */
+	outb(RST_CPU | SYS_RST, RST_CNT);
+}
+
+void do_board_reset(void)
+{
+	/* TODO: Would a warm_reset() suffice? */
+	do_cold_reset();
+}
-- 
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