From dffdea8a76e6ebc0f94ad25083983ae538f1d077 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 9 Dec 2020 23:04:29 +0100 Subject: soc/amd/cezanne: add caching setup in bootblock The code can likely be factored out to common code, but since I'm not entirely sure yet that there will be no differences, I'll copy for now instead. Change-Id: I5fc158518cf9534ab9727f3305abeb4b34049e76 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/48517 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/soc/amd/cezanne/include/soc/iomap.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/amd/cezanne/include') diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h index 4d47f7ed57..b377ee31fb 100644 --- a/src/soc/amd/cezanne/include/soc/iomap.h +++ b/src/soc/amd/cezanne/include/soc/iomap.h @@ -3,6 +3,9 @@ #ifndef AMD_CEZANNE_IOMAP_H #define AMD_CEZANNE_IOMAP_H +/* MMIO Ranges */ +#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) + /* I/O Ranges */ #define NCP_ERR 0x00f0 #define SMB_BASE_ADDR 0x0b00 -- cgit v1.2.3