From 7f3f52d7c6551e5b218404dfb0f01a99ee62c043 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 3 Mar 2021 18:56:41 +0100 Subject: soc/amd/cezanne: add SMU support BUG=b:181766974 Signed-off-by: Felix Held Change-Id: I5b9b4c3d57945ea7c3287cf47f3d9704f42ff24b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51233 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/soc/amd/cezanne/include/soc/smu.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 src/soc/amd/cezanne/include/soc/smu.h (limited to 'src/soc/amd/cezanne/include') diff --git a/src/soc/amd/cezanne/include/soc/smu.h b/src/soc/amd/cezanne/include/soc/smu.h new file mode 100644 index 0000000000..560c9e4e5e --- /dev/null +++ b/src/soc/amd/cezanne/include/soc/smu.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_CEZANNE_SMU_H +#define AMD_CEZANNE_SMU_H + +/* + * SMU mailbox register offsets in indirect address space accessed by an index/data pair in + * D0F00 config space. + */ +#define REG_ADDR_MESG_ID 0x3b10528 +#define REG_ADDR_MESG_RESP 0x3b10564 +#define REG_ADDR_MESG_ARGS_BASE 0x3b10998 + +#define SMU_NUM_ARGS 6 + +enum smu_message_id { + SMC_MSG_S3ENTRY = 0x0b, +}; + +/* + * Request the SMU put system into S3, S4, or S5. On entry, SlpTyp determines S-State and + * SlpTypeEn gets set by the SMU. Function does not return if successful. + */ +void smu_sx_entry(void); + +#endif /* AMD_CEZANNE_SMU_H */ -- cgit v1.2.3