From 6662fe60e1022e293519d098af8c22001991e9b4 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Mon, 21 Jun 2021 09:22:13 -0600 Subject: soc/amd/cezanne: Init eSPI early if required If the NO_EARLY_BOOTBLOCK_POSTCODES config option is enabled, configure eSPI as early as possible in the x86 boot sequence. We found that there are situations that can cause the system to hang if there are any port80h postcodes sent out before eSPI is initialized. BUG=b:191370340 TEST=Build & Boot with and without NO_EARLY_BOOTBLOCK_POSTCODES enabled. Signed-off-by: Martin Roth Change-Id: I0badb1c529e96ee4f81134287db53ce32473de6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/55732 Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- src/soc/amd/cezanne/include/soc/southbridge.h | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/amd/cezanne/include') diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index 0ed5f33f22..386d3c1e87 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -105,6 +105,7 @@ #define I2C_PAD_CTRL_SPARE0 BIT(17) #define I2C_PAD_CTRL_SPARE1 BIT(18) +void configure_port80_routing_early(void); void fch_pre_init(void); void fch_early_init(void); void fch_init(void *chip_info); -- cgit v1.2.3