From 03a4bfc54d6a467da1ba89ddc9e68e6637f90938 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 10 Mar 2021 23:29:11 +0100 Subject: soc/amd/common/block/smu: rename mailbox register defines Since we have the SMN access block now, rename the SMU mailbox interface registers to clarify that those are in the SMN register space. Signed-off-by: Felix Held Change-Id: Ic5b7093f99eabd3c29610072b186ed156f335bd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51400 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/soc/amd/cezanne/include/soc/smu.h | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) (limited to 'src/soc/amd/cezanne/include') diff --git a/src/soc/amd/cezanne/include/soc/smu.h b/src/soc/amd/cezanne/include/soc/smu.h index 560c9e4e5e..9216a38e8b 100644 --- a/src/soc/amd/cezanne/include/soc/smu.h +++ b/src/soc/amd/cezanne/include/soc/smu.h @@ -3,13 +3,10 @@ #ifndef AMD_CEZANNE_SMU_H #define AMD_CEZANNE_SMU_H -/* - * SMU mailbox register offsets in indirect address space accessed by an index/data pair in - * D0F00 config space. - */ -#define REG_ADDR_MESG_ID 0x3b10528 -#define REG_ADDR_MESG_RESP 0x3b10564 -#define REG_ADDR_MESG_ARGS_BASE 0x3b10998 +/* SMU mailbox register offsets in SMN */ +#define SMN_SMU_MESG_ID 0x3b10528 +#define SMN_SMU_MESG_RESP 0x3b10564 +#define SMN_SMU_MESG_ARGS_BASE 0x3b10998 #define SMU_NUM_ARGS 6 -- cgit v1.2.3