From 8d0a609e6d1bfb48de781e7223f73ff979d0ce2e Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Thu, 14 Jan 2021 01:40:50 +0100
Subject: soc,vendorcode/amd/cezanne: add basic FSP integration

This is a trimmed-down version of the Cezanne FSP integration code, so
for example the UPD definitions are empty, which will be addressed
later. Since coreboot just leaves the UPD values at their default, this
is not a problem during the initial platform bring-up.

Change-Id: Ie0fc30120c2455aa2160708251e9d2f229984305
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
---
 src/soc/amd/cezanne/fsp_params.c | 7 +++++++
 1 file changed, 7 insertions(+)
 create mode 100644 src/soc/amd/cezanne/fsp_params.c

(limited to 'src/soc/amd/cezanne/fsp_params.c')

diff --git a/src/soc/amd/cezanne/fsp_params.c b/src/soc/amd/cezanne/fsp_params.c
new file mode 100644
index 0000000000..d3f9fcf555
--- /dev/null
+++ b/src/soc/amd/cezanne/fsp_params.c
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <fsp/api.h>
+
+void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
+{
+}
-- 
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